From 49296f1f48251945635fcebf562331b5ca5eb9c5 Mon Sep 17 00:00:00 2001
From: Nate Begeman <natebegeman@mac.com>
Date: Wed, 31 Aug 2005 01:58:39 +0000
Subject: [PATCH] Enable generation of AssertSext and AssertZext in the PPC
 backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23168 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCISelLowering.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index dad4c9fd2ec..fd9233f229c 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -214,8 +214,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         MF.addLiveIn(GPR[GPR_idx]);
         argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
                                             GPR[GPR_idx], MVT::i32);
-        if (ObjectVT != MVT::i32)
-          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
+        if (ObjectVT != MVT::i32) {
+          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
+                                                       : ISD::AssertZext;
+          argt = DAG.getNode(AssertOp, MVT::i32, argt, 
+                             DAG.getValueType(ObjectVT));
+          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
+        }
       } else {
         needsLoad = true;
       }