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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
convert the last 4 X86ISD nodes that should have memoperands to have them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1168,11 +1168,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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// that are not a MemSDNode, and thus don't have proper addrspace info.
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Parent->getOpcode() != ISD::PREFETCH &&
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Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
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Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores.
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Parent->getOpcode() != X86ISD::FLD &&
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Parent->getOpcode() != X86ISD::FILD &&
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Parent->getOpcode() != X86ISD::FILD_FLAG &&
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Parent->getOpcode() != X86ISD::FST) {
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Parent->getOpcode() != ISD::INTRINSIC_VOID) { // nontemporal stores.
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unsigned AddrSpace =
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cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
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// AddrSpace 256 -> GS, 257 -> FS.
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@ -6321,9 +6321,8 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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EVT SrcVT = Op.getOperand(0).getValueType();
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if (SrcVT.isVector()) {
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if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
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if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64)
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return Op;
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}
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return SDValue();
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}
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@ -6355,16 +6354,27 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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SDValue StackSlot,
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SelectionDAG &DAG) const {
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// Build the FILD
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DebugLoc dl = Op.getDebugLoc();
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DebugLoc DL = Op.getDebugLoc();
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SDVTList Tys;
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bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
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if (useSSE)
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Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
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else
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Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
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unsigned ByteSize = SrcVT.getSizeInBits()/8;
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int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
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MachineMemOperand *MMO =
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, ByteSize, ByteSize);
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SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
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SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
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Tys, Ops, array_lengthof(Ops));
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SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
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X86ISD::FILD, DL,
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Tys, Ops, array_lengthof(Ops),
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SrcVT, MMO);
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if (useSSE) {
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Chain = Result.getValue(1);
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@ -6380,8 +6390,15 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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SDValue Ops[] = {
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Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
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};
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Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
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Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
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MachineMemOperand *MMO =
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOStore, 8, 8);
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Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
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Ops, array_lengthof(Ops),
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Op.getValueType(), MMO);
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Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
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MachinePointerInfo::getFixedStack(SSFI),
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false, false, 0);
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}
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@ -6564,9 +6581,16 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
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// DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
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// we must be careful to do the computation in x87 extended precision, not
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// in SSE. (The generic code can't know it's OK to do this, or how to.)
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int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
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MachineMemOperand *MMO =
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, 8, 8);
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SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
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SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
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SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
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SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
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MVT::i64, MMO);
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APInt FF(32, 0x5F800000ULL);
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@ -6640,16 +6664,22 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
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SDValue Chain = DAG.getEntryNode();
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SDValue Value = Op.getOperand(0);
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if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
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EVT TheVT = Op.getOperand(0).getValueType();
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if (isScalarFPTypeInSSEReg(TheVT)) {
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assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
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Chain = DAG.getStore(Chain, DL, Value, StackSlot,
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MachinePointerInfo::getFixedStack(SSFI),
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false, false, 0);
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SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
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SDValue Ops[] = {
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Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
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Chain, StackSlot, DAG.getValueType(TheVT)
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};
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Value = DAG.getNode(X86ISD::FLD, DL, Tys, Ops, 3);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, MemSize, MemSize);
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Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
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DstTy, MMO);
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Chain = Value.getValue(1);
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SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
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StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
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@ -57,26 +57,6 @@ namespace llvm {
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/// corresponds to X86::PSRLDQ.
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FSRL,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// CALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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@ -309,7 +289,27 @@ namespace llvm {
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/// and token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM
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FP_TO_INT64_IN_MEM,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST
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// WARNING: Do not add anything in the end unless you want the node to
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// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
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@ -32,13 +32,15 @@ def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
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[SDNPHasChain, SDNPInFlag, SDNPMayStore,
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SDNPMemOperand]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain, SDNPMayLoad]>;
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad,
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SDNPMemOperand]>;
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def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
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