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LiveVariables::VarInfo contains an AliveBlocks BitVector, which has as many
entries as there are basic blocks in the function. LiveVariables::getVarInfo creates a VarInfo struct for every register in the function, leading to quadratic space use. This patch changes the BitVector to a SparseBitVector, which doesn't help the worst-case memory use but does reduce the actual use in very long functions with short-lived variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72426 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,6 +33,7 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseBitVector.h"
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namespace llvm {
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namespace llvm {
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@ -75,7 +76,7 @@ public:
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/// through. This is a bit set which uses the basic block number as an
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/// through. This is a bit set which uses the basic block number as an
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/// index.
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/// index.
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///
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///
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BitVector AliveBlocks;
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SparseBitVector<> AliveBlocks;
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/// NumUses - Number of uses of this register across the entire function.
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/// NumUses - Number of uses of this register across the entire function.
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///
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///
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@ -422,7 +422,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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// If the kill happens after the definition, we have an intra-block
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// If the kill happens after the definition, we have an intra-block
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// live range.
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// live range.
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if (killIdx > defIndex) {
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if (killIdx > defIndex) {
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assert(vi.AliveBlocks.none() &&
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assert(vi.AliveBlocks.empty() &&
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"Shouldn't be alive across any blocks!");
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"Shouldn't be alive across any blocks!");
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LiveRange LR(defIndex, killIdx, ValNo);
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LiveRange LR(defIndex, killIdx, ValNo);
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interval.addRange(LR);
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interval.addRange(LR);
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@ -443,10 +443,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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// Iterate over all of the blocks that the variable is completely
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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// live interval.
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for (int i = vi.AliveBlocks.find_first(); i != -1;
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for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
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i = vi.AliveBlocks.find_next(i)) {
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E = vi.AliveBlocks.end(); I != E; ++I) {
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LiveRange LR(getMBBStartIdx(i),
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LiveRange LR(getMBBStartIdx(*I),
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getMBBEndIdx(i)+1, // MBB ends at -1.
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getMBBEndIdx(*I)+1, // MBB ends at -1.
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ValNo);
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ValNo);
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interval.addRange(LR);
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interval.addRange(LR);
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DOUT << " +" << LR;
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DOUT << " +" << LR;
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@ -52,8 +52,9 @@ void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
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void LiveVariables::VarInfo::dump() const {
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void LiveVariables::VarInfo::dump() const {
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cerr << " Alive in blocks: ";
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cerr << " Alive in blocks: ";
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for (int i = AliveBlocks.find_first(); i != -1; i = AliveBlocks.find_next(i))
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for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
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cerr << i << ", ";
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E = AliveBlocks.end(); I != E; ++I)
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cerr << *I << ", ";
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cerr << "\n Killed by:";
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cerr << "\n Killed by:";
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if (Kills.empty())
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if (Kills.empty())
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cerr << " No instructions.\n";
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cerr << " No instructions.\n";
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@ -75,9 +76,7 @@ LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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else
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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}
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VarInfo &VI = VirtRegInfo[RegIdx];
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return VirtRegInfo[RegIdx];
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VI.AliveBlocks.resize(MF->getNumBlockIDs());
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return VI;
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}
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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@ -96,11 +95,11 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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if (MBB == DefBlock) return; // Terminate recursion
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if (MBB == DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks[BBNum])
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if (VRInfo.AliveBlocks.test(BBNum))
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return; // We already know the block is live
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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VRInfo.AliveBlocks.set(BBNum);
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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E = MBB->pred_rend(); PI != E; ++PI)
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E = MBB->pred_rend(); PI != E; ++PI)
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@ -163,7 +162,7 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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// Add a new kill entry for this basic block. If this virtual register is
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// Add a new kill entry for this basic block. If this virtual register is
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// already marked as alive in this basic block, that means it is alive in at
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// already marked as alive in this basic block, that means it is alive in at
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// least one of the successor blocks, it's not a kill.
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// least one of the successor blocks, it's not a kill.
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if (!VRInfo.AliveBlocks[BBNum])
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if (!VRInfo.AliveBlocks.test(BBNum))
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VRInfo.Kills.push_back(MI);
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them as "known live".
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// Update all dominating blocks to mark them as "known live".
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@ -175,7 +174,7 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
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void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
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VarInfo &VRInfo = getVarInfo(Reg);
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VarInfo &VRInfo = getVarInfo(Reg);
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if (VRInfo.AliveBlocks.none())
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if (VRInfo.AliveBlocks.empty())
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// If vr is not alive in any block, then defaults to dead.
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// If vr is not alive in any block, then defaults to dead.
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VRInfo.Kills.push_back(MI);
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VRInfo.Kills.push_back(MI);
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}
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}
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@ -334,8 +334,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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// Is it alive in this successor?
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// Is it alive in this successor?
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unsigned SuccIdx = SuccMBB->getNumber();
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unsigned SuccIdx = SuccMBB->getNumber();
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if (SuccIdx < InRegVI.AliveBlocks.size() &&
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if (InRegVI.AliveBlocks.test(SuccIdx)) {
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InRegVI.AliveBlocks[SuccIdx]) {
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ValueIsLive = true;
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ValueIsLive = true;
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break;
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break;
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}
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}
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@ -407,8 +406,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
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// This vreg no longer lives all of the way through opBlock.
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// This vreg no longer lives all of the way through opBlock.
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unsigned opBlockNum = opBlock.getNumber();
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unsigned opBlockNum = opBlock.getNumber();
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if (opBlockNum < InRegVI.AliveBlocks.size())
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InRegVI.AliveBlocks.reset(opBlockNum);
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InRegVI.AliveBlocks[opBlockNum] = false;
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}
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}
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}
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}
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