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R600/SI: Rework MUBUF store instructions
The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -115,7 +115,6 @@ enum {
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RET_FLAG,
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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BUFFER_STORE,
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DWORDADDR,
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FRACT,
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FMAX,
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@ -25,6 +25,8 @@
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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@ -72,9 +74,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i64, Custom);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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@ -214,10 +213,38 @@ SDValue SITargetLowering::LowerFormalArguments(
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MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const {
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MachineBasicBlock::iterator I = *MI;
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switch (MI->getOpcode()) {
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default:
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return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case AMDGPU::BRANCH: return BB;
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case AMDGPU::SI_ADDR64_RSRC: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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unsigned SuperReg = MI->getOperand(0).getReg();
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unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
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.addOperand(MI->getOperand(1));
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
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.addImm(0);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
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.addImm(RSRC_DATA_FORMAT >> 32);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
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.addReg(SubRegHiLo)
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.addImm(AMDGPU::sub0)
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.addReg(SubRegHiHi)
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.addImm(AMDGPU::sub1);
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BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
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.addReg(SubRegLo)
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.addImm(AMDGPU::sub0_sub1)
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.addReg(SubRegHi)
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.addImm(AMDGPU::sub2_sub3);
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MI->eraseFromParent();
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break;
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}
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}
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return BB;
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}
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@ -239,7 +266,6 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::STORE: return LowerSTORE(Op, DAG);
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}
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return SDValue();
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}
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@ -338,32 +364,6 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
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return Chain;
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}
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
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SDValue Chain = Op.getOperand(0);
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SDValue Value = Op.getOperand(1);
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SDValue VirtualAddress = Op.getOperand(2);
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SDLoc DL(Op);
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if (StoreNode->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS) {
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return SDValue();
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}
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SDValue Zero = DAG.getConstant(0, MVT::i64);
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SDValue Format = DAG.getConstant(RSRC_DATA_FORMAT, MVT::i64);
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SDValue SrcSrc = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, Zero, Format);
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SDValue Ops[2];
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Ops[0] = DAG.getNode(AMDGPUISD::BUFFER_STORE, DL, MVT::Other, Chain,
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Value, SrcSrc, VirtualAddress);
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Ops[1] = Chain;
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return DAG.getMergeValues(Ops, 2, DL);
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}
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SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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@ -24,7 +24,6 @@ class SITargetLowering : public AMDGPUTargetLowering {
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const SIInstrInfo * TII;
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const TargetRegisterInfo * TRI;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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@ -26,10 +26,6 @@ def HI32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
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}]>;
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def SIbuffer_store : SDNode<"AMDGPUISD::BUFFER_STORE",
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SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayStore]>;
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def IMM8bitDWORD : ImmLeaf <
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i32, [{
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return (Imm & ~0x3FC) == 0;
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@ -327,16 +323,14 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
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ValueType VT> :
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MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr),
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name#" $vdata, $srsrc + $vaddr",
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[(SIbuffer_store (VT vdataClass:$vdata), (i128 SReg_128:$srsrc),
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(i64 VReg_64:$vaddr))]> {
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MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
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name#" $vdata, $srsrc + $vaddr + $offset",
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[]> {
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let mayLoad = 0;
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let mayStore = 1;
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// Encoding
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let offset = 0;
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let offen = 0;
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let idxen = 0;
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let glc = 0;
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@ -416,7 +416,10 @@ def BUFFER_STORE_DWORD : MUBUF_Store_Helper <
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def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
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0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, i64
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>;
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//def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>;
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def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
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0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32
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>;
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//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>;
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//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>;
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//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>;
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@ -1200,6 +1203,19 @@ def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
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} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
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// This psuedo instruction takes a pointer as input and outputs a resource
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// constant that can be used with the ADDR64 MUBUF instructions.
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let usesCustomInserter = 1 in {
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def SI_ADDR64_RSRC : InstSI <
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(outs SReg_128:$srsrc),
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(ins SReg_64:$ptr),
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"", []
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>;
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} // end usesCustomInserter
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} // end IsCodeGenOnly, isPseudo
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def : Pat<
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@ -1591,6 +1607,27 @@ defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
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defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
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//===----------------------------------------------------------------------===//
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// MUBUF Patterns
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//===----------------------------------------------------------------------===//
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multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt> {
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def : Pat <
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(global_store vt:$value, i64:$ptr),
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(Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0)
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>;
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def : Pat <
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(global_store vt:$value, (add i64:$ptr, i64:$offset)),
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(Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0)
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>;
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}
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defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32>;
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defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64>;
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defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32>;
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/********** ====================== **********/
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/********** Indirect adressing **********/
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/********** ====================== **********/
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