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Encoding for ARM-mode VADD.F32 instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-12 21:22:40 +00:00
parent 2ab36d3502
commit 499e886fe6
2 changed files with 16 additions and 3 deletions
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2
lib/Target/ARM/ARMInstrFormats.td
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@ -1288,6 +1288,8 @@ class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
bits<4> p;
let Inst{31-28} = p;
let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p));
let AsmString = !strconcat(opc, "${p}", asm);

17
lib/Target/ARM/ARMInstrVFP.td
View File

@ -146,9 +146,20 @@ def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
[(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
bits<5> Sd;
bits<5> Sn;
bits<5> Sm;
let Inst{3-0} = Sm{4-1};
let Inst{5} = Sm{0};
let Inst{19-16} = Sn{4-1};
let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
// These are encoded as unary instructions.
let Defs = [FPSCR] in {