From 49bd37d369e1124fa0844f60bf80ffb9247d4519 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 7 Mar 2008 20:13:51 +0000 Subject: [PATCH] Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work with 32 or 64-bit operands/results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrInfo.td | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index a0b2512c6df..a0f6ccc2b4c 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -20,9 +20,6 @@ include "PPCInstrFormats.td" def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx SDTCisVT<0, f64>, SDTCisPtrTy<1> ]>; -def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl - SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> -]>; def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; @@ -84,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift // amounts. These nodes are generated by the multi-precision shift code. -def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; -def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; -def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; +def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>; +def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>; +def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>; def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,