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Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mihai Popa 2013-08-06 15:52:36 +00:00
parent df66ff09bc
commit 4a378b95aa
4 changed files with 19 additions and 20 deletions
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8
lib/Target/ARM/ARMInstrThumb2.td
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@ -3907,17 +3907,17 @@ def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
/* from coprocessor to ARM core register */ /* from coprocessor to ARM core register */
def t2MRC : t2MovRCopro<0b1110, "mrc", 1, def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
c_imm:$CRm, imm0_7:$opc2), []>; c_imm:$CRm, imm0_7:$opc2), []>;
def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
(t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
c_imm:$CRm, 0, pred:$p)>; c_imm:$CRm, 0, pred:$p)>;
def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
(outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
c_imm:$CRm, imm0_7:$opc2), []>; c_imm:$CRm, imm0_7:$opc2), []>;
def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm", def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
(t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
c_imm:$CRm, 0, pred:$p)>; c_imm:$CRm, 0, pred:$p)>;
def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),

2
lib/Target/ARM/ARMRegisterInfo.td
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@ -215,7 +215,7 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
// GPRs without the PC but with APSR. Some instructions allow accessing the // GPRs without the PC but with APSR. Some instructions allow accessing the
// APSR, while actually encoding PC in the register field. This is usefull // APSR, while actually encoding PC in the register field. This is usefull
// for assembly and disassembly only. // for assembly and disassembly only.
def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add GPR, APSR_NZCV)> { def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();

8
test/MC/ARM/basic-arm-instructions.s
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@ -1076,20 +1076,16 @@ Lforward:
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
mrc p14, #0, r1, c1, c2, #4 mrc p14, #0, r1, c1, c2, #4
mrc p15, #7, apsr_nzcv, c15, c6, #6 mrc p15, #7, apsr_nzcv, c15, c6, #6
mrc p15, #7, pc, c15, c6, #6
mrc2 p14, #0, r1, c1, c2, #4 mrc2 p14, #0, r1, c1, c2, #4
mrc2 p10, #7, apsr_nzcv, c15, c0, #1 mrc2 p10, #7, apsr_nzcv, c15, c0, #1
mrc2 p10, #7, pc, c15, c0, #1
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee] @ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
@ CHECK: mrc p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe] @ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
@ CHECK: mrc2 p10, #7, pc, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
mrceq p15, #7, pc, c15, c6, #6 mrceq p15, #7, apsr_nzcv, c15, c6, #6
@ CHECK: mrceq p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e] @ CHECK: mrceq p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0x0e]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ MRRC/MRRC2 @ MRRC/MRRC2

21
test/MC/ARM/basic-thumb2-instructions.s
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@ -1347,16 +1347,19 @@ _func:
@ MRC/MRC2 @ MRC/MRC2
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
mrc p14, #0, r1, c1, c2, #4 mrc p14, #0, r1, c1, c2, #4
mrc2 p14, #0, r1, c1, c2, #4 mrc p15, #7, apsr_nzcv, c15, c6, #6
mrc p11, #1, r1, c2, c2 mrc p11, #1, r1, c2, c2
mrc2 p12, #3, r3, c3, c4 mrc2 p12, #3, r3, c3, c4
mrc2 p14, #0, r1, c1, c2, #4
@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] mrc2 p10, #7, apsr_nzcv, c15, c0, #1
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
@ CHECK: mrc p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b] @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c] @ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xff,0xee,0xd6,0xff]
@ CHECK: mrc p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b]
@ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xfa]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ MRRC/MRRC2 @ MRRC/MRRC2
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------