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Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,

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allowing redundant and's to be eliminated by the dag combiner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25800 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-30 03:51:45 +00:00
parent 5c413bc451
commit 4a397e0e94
2 changed files with 52 additions and 0 deletions
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26
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -57,6 +57,14 @@ namespace {
public:
SparcV8TargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
uint64_t Mask,
MVIZFnPtr MVIZ) const;
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
virtual std::pair<SDOperand, SDOperand>
@ -191,6 +199,24 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
bool SparcV8TargetLowering::
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
MVIZFnPtr MVIZ) const {
switch (Op.getOpcode()) {
default: return false;
case V8ISD::SELECT_ICC:
case V8ISD::SELECT_FCC:
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
// These operations are masked zero if both the left and the right are zero.
return MVIZ(Op.getOperand(0), Mask, *this) &&
MVIZ(Op.getOperand(1), Mask, *this);
}
}
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.

26
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -57,6 +57,14 @@ namespace {
public:
SparcV8TargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
uint64_t Mask,
MVIZFnPtr MVIZ) const;
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
virtual std::pair<SDOperand, SDOperand>
@ -191,6 +199,24 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
bool SparcV8TargetLowering::
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
MVIZFnPtr MVIZ) const {
switch (Op.getOpcode()) {
default: return false;
case V8ISD::SELECT_ICC:
case V8ISD::SELECT_FCC:
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
// These operations are masked zero if both the left and the right are zero.
return MVIZ(Op.getOperand(0), Mask, *this) &&
MVIZ(Op.getOperand(1), Mask, *this);
}
}
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.