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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78136 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
c2a9eeb273
commit
4a3d35abef
@ -1284,7 +1284,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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MVT HalfVT;
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unsigned Opc = 0;
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switch (VT.getVectorElementType().getSimpleVT()) {
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default: assert(false && "unhandled VDUP splat type");
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default: llvm_unreachable("unhandled VDUP splat type");
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case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
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case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
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case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
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@ -1304,6 +1304,62 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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break;
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}
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case ARMISD::VLD2D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD2D type");
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case MVT::v8i8: Opc = ARM::VLD2d8; break;
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case MVT::v4i16: Opc = ARM::VLD2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD2d32; break;
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case MVT::v1i64: Opc = ARM::VLD2d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
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}
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case ARMISD::VLD3D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD3D type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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case MVT::v4i16: Opc = ARM::VLD3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD3d32; break;
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case MVT::v1i64: Opc = ARM::VLD3d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
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}
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case ARMISD::VLD4D: {
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MVT VT = Op.getValueType();
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc;
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switch (VT.getSimpleVT()) {
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default: llvm_unreachable("unhandled VLD4D type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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case MVT::v1i64: Opc = ARM::VLD4d64; break;
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}
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
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std::vector<MVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
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}
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}
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return SelectCode(Op);
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@ -1323,7 +1323,7 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
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}
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static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode, unsigned NumVecs) {
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unsigned Opcode) {
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SDNode *Node = Op.getNode();
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MVT VT = Node->getValueType(0);
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DebugLoc dl = Op.getDebugLoc();
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@ -1332,25 +1332,8 @@ static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
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return SDValue(); // unimplemented
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SDValue Ops[] = { Node->getOperand(0),
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Node->getOperand(1) };
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
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SDValue Result = DAG.getNode(Opcode, dl, Tys, Ops, 2);
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static const unsigned VLDRegs[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3
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};
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SmallVector<SDValue, 4> ResultVals;
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SDValue Chain = Result.getValue(0);
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SDValue Flag = Result.getValue(1);
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for (unsigned N = 0; N < NumVecs; ++N) {
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Chain = DAG.getCopyFromReg(Chain, dl, VLDRegs[N], VT, Flag).getValue(1);
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ResultVals.push_back(Chain.getValue(0));
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Flag = Chain.getValue(2);
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}
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ResultVals.push_back(Chain);
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return DAG.getNode(ISD::MERGE_VALUES, dl, Node->getVTList(),
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ResultVals.data(), NumVecs + 1);
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Node->getOperand(2) };
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return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
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}
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SDValue
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@ -1359,13 +1342,13 @@ ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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switch (IntNo) {
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case Intrinsic::arm_neon_vld2i:
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case Intrinsic::arm_neon_vld2f:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D, 2);
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
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case Intrinsic::arm_neon_vld3i:
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case Intrinsic::arm_neon_vld3f:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D, 3);
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
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case Intrinsic::arm_neon_vld4i:
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case Intrinsic::arm_neon_vld4f:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D, 4);
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
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case Intrinsic::arm_neon_vst2i:
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case Intrinsic::arm_neon_vst2f:
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case Intrinsic::arm_neon_vst3i:
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@ -68,13 +68,18 @@ def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
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def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
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SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
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def SDTARMVLD : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD,
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
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def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD,
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
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def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD,
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[SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
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def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
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def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
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def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
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def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
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[SDNPHasChain, SDNPMayLoad]>;
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def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
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[SDNPHasChain, SDNPMayLoad]>;
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def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
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[SDNPHasChain, SDNPMayLoad]>;
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//===----------------------------------------------------------------------===//
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// NEON operand definitions
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@ -183,6 +188,37 @@ def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
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def VLD2d8 : VLD2D<"vld2.8">;
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def VLD2d16 : VLD2D<"vld2.16">;
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def VLD2d32 : VLD2D<"vld2.32">;
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def VLD2d64 : VLD2D<"vld2.64">;
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// VLD3 : Vector Load (multiple 3-element structures)
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class VLD3D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
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def VLD3d8 : VLD3D<"vld3.8">;
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def VLD3d16 : VLD3D<"vld3.16">;
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def VLD3d32 : VLD3D<"vld3.32">;
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def VLD3d64 : VLD3D<"vld3.64">;
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// VLD4 : Vector Load (multiple 4-element structures)
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class VLD4D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr),
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
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def VLD4d8 : VLD4D<"vld4.8">;
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def VLD4d16 : VLD4D<"vld4.16">;
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def VLD4d32 : VLD4D<"vld4.32">;
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def VLD4d64 : VLD4D<"vld4.64">;
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//===----------------------------------------------------------------------===//
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// NEON pattern fragments
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@ -93,6 +93,8 @@ bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Call NEON pre-alloc pass here.
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// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
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PM.add(createARMLoadStoreOptimizationPass(true));
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