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[AVX512] Bring back vector-shuffle lowering support through broadcasts
Ffter commit at rev219046 512-bit broadcasts lowering become non-optimal. Most of tests on broadcasting and embedded broadcasting were changed and they doesn’t produce efficient code.
Example below is from commit changes (it’s the first test from test/CodeGen/X86/avx512-vbroadcast.ll):
define <16 x i32> @_inreg16xi32(i32 %a) {
; CHECK-LABEL: _inreg16xi32:
; CHECK: ## BB#0:
-; CHECK-NEXT: vpbroadcastd %edi, %zmm0
+; CHECK-NEXT: vmovd %edi, %xmm0
+; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0
+; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
; CHECK-NEXT: retq
%b = insertelement <16 x i32> undef, i32 %a, i32 0
%c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
ret <16 x i32> %c
}
Here, 256-bit broadcast was generated instead of 512-bit one.
In this patch
1) I added vector-shuffle lowering through broadcasts
2) Removed asserts and branches likes because this is incorrect
- assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
3) Fixed lowering tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220774 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
81ae170379
commit
4a52493457
@ -10231,7 +10231,6 @@ static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
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assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
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@ -10247,7 +10246,6 @@ static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
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assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
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// FIXME: Implement direct support for this type!
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return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
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@ -10299,6 +10297,11 @@ static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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assert(Subtarget->hasAVX512() &&
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"Cannot lower 512-bit vectors w/ basic ISA!");
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// Check for being able to broadcast a single element.
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if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
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Mask, Subtarget, DAG))
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return Broadcast;
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// Dispatch to each element type for lowering. If we don't have supprot for
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// specific element type shuffles at 512 bits, immediately split them and
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// lower them. Each lowering routine of a given type is allowed to assume that
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@ -10309,13 +10312,9 @@ static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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case MVT::v16f32:
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return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v8i64:
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if (Subtarget->hasDQI())
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return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
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break;
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return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v16i32:
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if (Subtarget->hasDQI())
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return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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break;
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return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
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case MVT::v32i16:
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if (Subtarget->hasBWI())
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return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
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@ -711,6 +711,16 @@ def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
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def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
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(VBROADCASTSDZrr VR128X:$src)>;
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def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
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(VBROADCASTSSZrr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
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def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
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(VBROADCASTSDZrr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
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def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
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(VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
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def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
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(VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
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def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
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(VBROADCASTSSZrr VR128X:$src)>;
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def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
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@ -453,10 +453,7 @@ entry:
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define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
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; CHECK-LABEL: andqbrst:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovq (%rdi), %xmm1
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; CHECK-NEXT: vpbroadcastq %xmm1, %ymm1
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; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
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; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: vpandq (%rdi){1to8}, %zmm0, %zmm0
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; CHECK-NEXT: retq
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entry:
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%a = load i64* %ap, align 8
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@ -3,9 +3,7 @@
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define <16 x i32> @_inreg16xi32(i32 %a) {
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; CHECK-LABEL: _inreg16xi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovd %edi, %xmm0
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; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0
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; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vpbroadcastd %edi, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <16 x i32> undef, i32 %a, i32 0
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%c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
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@ -15,9 +13,7 @@ define <16 x i32> @_inreg16xi32(i32 %a) {
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define <8 x i64> @_inreg8xi64(i64 %a) {
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; CHECK-LABEL: _inreg8xi64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovq %rdi, %xmm0
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; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0
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; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vpbroadcastq %rdi, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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@ -27,9 +23,7 @@ define <8 x i64> @_inreg8xi64(i64 %a) {
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define <16 x float> @_inreg16xfloat(float %a) {
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; CHECK-LABEL: _inreg16xfloat:
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; CHECK: ## BB#0:
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; CHECK-NEXT: ## kill: XMM0<def> XMM0<kill> ZMM0<def>
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; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
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; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <16 x float> undef, float %a, i32 0
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%c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
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@ -39,9 +33,7 @@ define <16 x float> @_inreg16xfloat(float %a) {
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define <8 x double> @_inreg8xdouble(double %a) {
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; CHECK-LABEL: _inreg8xdouble:
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; CHECK: ## BB#0:
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; CHECK-NEXT: ## kill: XMM0<def> XMM0<kill> ZMM0<def>
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; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
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; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vbroadcastsd %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = insertelement <8 x double> undef, double %a, i32 0
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%c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
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@ -51,8 +43,7 @@ define <8 x double> @_inreg8xdouble(double %a) {
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define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
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; CHECK-LABEL: _xmm16xi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0
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; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vpbroadcastd %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> zeroinitializer
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ret <16 x i32> %b
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@ -61,8 +52,7 @@ define <16 x i32> @_xmm16xi32(<16 x i32> %a) {
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define <16 x float> @_xmm16xfloat(<16 x float> %a) {
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; CHECK-LABEL: _xmm16xfloat:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
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; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
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; CHECK-NEXT: vbroadcastss %xmm0, %zmm0
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; CHECK-NEXT: retq
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%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> zeroinitializer
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ret <16 x float> %b
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@ -312,10 +312,7 @@ define <16 x i32> @test23(<16 x i32> %x, <16 x i32>* %y.ptr, <16 x i32> %x1, <16
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define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
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; CHECK-LABEL: test24:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovq (%rdi), %xmm2
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; CHECK-NEXT: vpbroadcastq %xmm2, %ymm2
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; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm2
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; CHECK-NEXT: vpcmpeqq %zmm2, %zmm0, %k1
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; CHECK-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k1
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; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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@ -330,10 +327,7 @@ define <8 x i64> @test24(<8 x i64> %x, <8 x i64> %x1, i64* %yb.ptr) nounwind {
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define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind {
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; CHECK-LABEL: test25:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovd (%rdi), %xmm2
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; CHECK-NEXT: vpbroadcastd %xmm2, %ymm2
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; CHECK-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm2
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; CHECK-NEXT: vpcmpled %zmm2, %zmm0, %k1
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; CHECK-NEXT: vpcmpled (%rdi){1to16}, %zmm0, %k1
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; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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@ -348,11 +342,8 @@ define <16 x i32> @test25(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1) nounwind
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define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32> %y1) nounwind {
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; CHECK-LABEL: test26:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovd (%rdi), %xmm3
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; CHECK-NEXT: vpbroadcastd %xmm3, %ymm3
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; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm3, %zmm3
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; CHECK-NEXT: vpcmpgtd %zmm3, %zmm0, %k1
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; CHECK-NEXT: vpcmpled %zmm1, %zmm2, %k1 {%k1}
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; CHECK-NEXT: vpcmpled %zmm1, %zmm2, %k1
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; CHECK-NEXT: vpcmpgtd (%rdi){1to16}, %zmm0, %k1 {%k1}
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; CHECK-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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@ -369,11 +360,8 @@ define <16 x i32> @test26(<16 x i32> %x, i32* %yb.ptr, <16 x i32> %x1, <16 x i32
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define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y1) nounwind {
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; CHECK-LABEL: test27:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovq (%rdi), %xmm3
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; CHECK-NEXT: vpbroadcastq %xmm3, %ymm3
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; CHECK-NEXT: vinserti64x4 $1, %ymm3, %zmm3, %zmm3
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; CHECK-NEXT: vpcmpleq %zmm3, %zmm0, %k1
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; CHECK-NEXT: vpcmpleq %zmm1, %zmm2, %k1 {%k1}
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; CHECK-NEXT: vpcmpleq %zmm1, %zmm2, %k1
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; CHECK-NEXT: vpcmpleq (%rdi){1to8}, %zmm0, %k1 {%k1}
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; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1}
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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@ -6,8 +6,7 @@ target triple = "x86_64-unknown-unknown"
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define <8 x double> @shuffle_v8f64_00000000(<8 x double> %a, <8 x double> %b) {
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; ALL-LABEL: shuffle_v8f64_00000000:
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; ALL: # BB#0:
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; ALL-NEXT: vbroadcastsd %xmm0, %ymm0
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; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
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; ALL-NEXT: vbroadcastsd %xmm0, %zmm0
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; ALL-NEXT: retq
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%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x double> %shuffle
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@ -729,8 +728,7 @@ define <8 x double> @shuffle_v8f64_f511235a(<8 x double> %a, <8 x double> %b) {
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define <8 x i64> @shuffle_v8i64_00000000(<8 x i64> %a, <8 x i64> %b) {
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; ALL-LABEL: shuffle_v8i64_00000000:
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; ALL: # BB#0:
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; ALL-NEXT: vpbroadcastq %xmm0, %ymm0
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; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
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; ALL-NEXT: vpbroadcastq %xmm0, %zmm0
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; ALL-NEXT: retq
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%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i64> %shuffle
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