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ARM SSAT instruction 5-bit immediate handling.

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The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-22 23:16:18 +00:00
parent 4428069f10
commit 4a5ffb399f
9 changed files with 38 additions and 24 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1726,8 +1726,6 @@ static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRd(insn))));
unsigned Pos = slice(insn, 20, 16);
if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
Pos += 1;
MI.addOperand(MCOperand::CreateImm(Pos));
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,