From 4a6855441c82b96a57fbfcdf41f8fef591c1cc62 Mon Sep 17 00:00:00 2001
From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Mon, 2 Dec 2013 04:55:42 +0000
Subject: [PATCH] Change the default of AsmWriterClassName and isMCAsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
---
include/llvm/Target/Target.td | 4 ++--
lib/Target/AArch64/AArch64.td | 10 ----------
lib/Target/ARM/ARM.td | 13 -------------
lib/Target/Hexagon/Hexagon.td | 10 ----------
lib/Target/MSP430/MSP430.td | 6 ------
lib/Target/Mips/Mips.td | 6 ------
lib/Target/NVPTX/NVPTX.td | 6 ------
lib/Target/PowerPC/PPC.td | 8 +-------
lib/Target/R600/AMDGPU.td | 10 ----------
lib/Target/Sparc/Sparc.td | 7 +++++++
lib/Target/SystemZ/SystemZ.td | 10 ----------
lib/Target/X86/X86.td | 2 --
lib/Target/XCore/XCore.td | 6 ------
13 files changed, 10 insertions(+), 88 deletions(-)
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 8871c5714c5..b592edcf3c3 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -949,7 +949,7 @@ class AsmWriter {
// AsmWriterClassName - This specifies the suffix to use for the asmwriter
// class. Generated AsmWriter classes are always prefixed with the target
// name.
- string AsmWriterClassName = "AsmPrinter";
+ string AsmWriterClassName = "InstPrinter";
// Variant - AsmWriters can be of multiple different variants. Variants are
// used to support targets that need to emit assembly code in ways that are
@@ -973,7 +973,7 @@ class AsmWriter {
// isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
// generation of the printInstruction() method. For MC printers, it takes
// an MCInstr* operand, otherwise it takes a MachineInstr*.
- bit isMCAsmWriter = 0;
+ bit isMCAsmWriter = 1;
}
def DefaultAsmWriter : AsmWriter;
diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
index 9c2c69a6593..6139d147a61 100644
--- a/lib/Target/AArch64/AArch64.td
+++ b/lib/Target/AArch64/AArch64.td
@@ -54,20 +54,10 @@ include "AArch64InstrInfo.td"
def AArch64InstrInfo : InstrInfo;
-//===----------------------------------------------------------------------===//
-// Assembly printer
-//===----------------------------------------------------------------------===//
-
-def A64InstPrinter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def AArch64 : Target {
let InstructionSet = AArch64InstrInfo;
- let AssemblyWriters = [A64InstPrinter];
}
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index ed827c47ceb..ca2ddfdff3b 100644
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -391,17 +391,6 @@ include "ARMInstrInfo.td"
def ARMInstrInfo : InstrInfo;
-
-//===----------------------------------------------------------------------===//
-// Assembly printer
-//===----------------------------------------------------------------------===//
-// ARM Uses the MC printer for asm output, so make sure the TableGen
-// AsmWriter bits get associated with the correct class.
-def ARMAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
@@ -409,6 +398,4 @@ def ARMAsmWriter : AsmWriter {
def ARM : Target {
// Pull in Instruction Info:
let InstructionSet = ARMInstrInfo;
-
- let AssemblyWriters = [ARMAsmWriter];
}
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td
index 568798c3a41..c1b6d45ce89 100644
--- a/lib/Target/Hexagon/Hexagon.td
+++ b/lib/Target/Hexagon/Hexagon.td
@@ -205,14 +205,6 @@ def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
-
-// Hexagon Uses the MC printer for assembler output, so make sure the TableGen
-// AsmWriter bits get associated with the correct class.
-def HexagonAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
@@ -220,6 +212,4 @@ def HexagonAsmWriter : AsmWriter {
def Hexagon : Target {
// Pull in Instruction Info:
let InstructionSet = HexagonInstrInfo;
-
- let AssemblyWriters = [HexagonAsmWriter];
}
diff --git a/lib/Target/MSP430/MSP430.td b/lib/Target/MSP430/MSP430.td
index c6796b3789a..dfea669f3ba 100644
--- a/lib/Target/MSP430/MSP430.td
+++ b/lib/Target/MSP430/MSP430.td
@@ -50,17 +50,11 @@ include "MSP430InstrInfo.td"
def MSP430InstrInfo : InstrInfo;
-def MSP430InstPrinter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Target Declaration
//===----------------------------------------------------------------------===//
def MSP430 : Target {
let InstructionSet = MSP430InstrInfo;
- let AssemblyWriters = [MSP430InstPrinter];
}
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td
index b8e3f39256d..c7ebdac1c05 100644
--- a/lib/Target/Mips/Mips.td
+++ b/lib/Target/Mips/Mips.td
@@ -96,11 +96,6 @@ def : Proc<"mips64", [FeatureMips64]>;
def : Proc<"mips64r2", [FeatureMips64r2]>;
def : Proc<"mips16", [FeatureMips16]>;
-def MipsAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
let MnemonicContainsDot = 1;
@@ -116,6 +111,5 @@ def MipsAsmParserVariant : AsmParserVariant {
def Mips : Target {
let InstructionSet = MipsInstrInfo;
let AssemblyParsers = [MipsAsmParser];
- let AssemblyWriters = [MipsAsmWriter];
let AssemblyParserVariants = [MipsAsmParserVariant];
}
diff --git a/lib/Target/NVPTX/NVPTX.td b/lib/Target/NVPTX/NVPTX.td
index 6183a755c32..d78b4e81a3e 100644
--- a/lib/Target/NVPTX/NVPTX.td
+++ b/lib/Target/NVPTX/NVPTX.td
@@ -57,12 +57,6 @@ def : Proc<"sm_35", [SM35]>;
def NVPTXInstrInfo : InstrInfo {
}
-def NVPTXAsmWriter : AsmWriter {
- bit isMCAsmWriter = 1;
- string AsmWriterClassName = "InstPrinter";
-}
-
def NVPTX : Target {
let InstructionSet = NVPTXInstrInfo;
- let AssemblyWriters = [NVPTXAsmWriter];
}
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index a8bb52d90dc..044740e4c75 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -285,11 +285,6 @@ def PPCInstrInfo : InstrInfo {
let isLittleEndianEncoding = 1;
}
-def PPCAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
def PPCAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
}
@@ -306,8 +301,7 @@ def PPCAsmParserVariant : AsmParserVariant {
def PPC : Target {
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
-
- let AssemblyWriters = [PPCAsmWriter];
+
let AssemblyParsers = [PPCAsmParser];
let AssemblyParserVariants = [PPCAsmParserVariant];
}
diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index 182235b27c4..36c41560915 100644
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -100,19 +100,9 @@ def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1;
}
-//===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
-//===----------------------------------------------------------------------===//
-def AMDGPUAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- int Variant = 0;
- bit isMCAsmWriter = 1;
-}
-
def AMDGPU : Target {
// Pull in Instruction Info:
let InstructionSet = AMDGPUInstrInfo;
- let AssemblyWriters = [AMDGPUAsmWriter];
}
// Include AMDGPU TD files
diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index 0df48f60e8f..097b565b88f 100644
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -66,6 +66,11 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+def SparcAsmWriter : AsmWriter {
+ string AsmWriterClassName = "AsmPrinter";
+ bit isMCAsmWriter = 0;
+}
+
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
@@ -73,4 +78,6 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
def Sparc : Target {
// Pull in Instruction Info:
let InstructionSet = SparcInstrInfo;
+
+ let AssemblyWriters = [SparcAsmWriter];
}
diff --git a/lib/Target/SystemZ/SystemZ.td b/lib/Target/SystemZ/SystemZ.td
index abf5c8eb320..5f829034902 100644
--- a/lib/Target/SystemZ/SystemZ.td
+++ b/lib/Target/SystemZ/SystemZ.td
@@ -52,15 +52,6 @@ def SystemZAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
}
-//===----------------------------------------------------------------------===//
-// Assembly writer
-//===----------------------------------------------------------------------===//
-
-def SystemZAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Top-level target declaration
//===----------------------------------------------------------------------===//
@@ -68,5 +59,4 @@ def SystemZAsmWriter : AsmWriter {
def SystemZ : Target {
let InstructionSet = SystemZInstrInfo;
let AssemblyParsers = [SystemZAsmParser];
- let AssemblyWriters = [SystemZAsmWriter];
}
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index ebe1a826266..d55178ea12d 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -396,12 +396,10 @@ def IntelAsmParserVariant : AsmParserVariant {
def ATTAsmWriter : AsmWriter {
string AsmWriterClassName = "ATTInstPrinter";
int Variant = 0;
- bit isMCAsmWriter = 1;
}
def IntelAsmWriter : AsmWriter {
string AsmWriterClassName = "IntelInstPrinter";
int Variant = 1;
- bit isMCAsmWriter = 1;
}
def X86 : Target {
diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td
index e9a6d88fd68..04a1dd5e95b 100644
--- a/lib/Target/XCore/XCore.td
+++ b/lib/Target/XCore/XCore.td
@@ -41,13 +41,7 @@ def : Proc<"xs1b-generic", []>;
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
-def XCoreAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
def XCore : Target {
// Pull in Instruction Info:
let InstructionSet = XCoreInstrInfo;
- let AssemblyWriters = [XCoreAsmWriter];
}