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Use the autogenerated matcher for ADD/SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23510 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -767,16 +767,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
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Select(N->getOperand(0)));
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return SDOperand(N, 0);
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case ISD::ADD:
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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}
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return SDOperand(N, 0);
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case ISD::FADD: {
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MVT::ValueType Ty = N->getValueType(0);
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if (!NoExcessFPPrecision) { // Match FMA ops
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@ -803,26 +793,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::SUB: {
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unsigned Imm;
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if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
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if (0 == Imm)
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CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, Select(N->getOperand(1)));
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else
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CurDAG->SelectNodeTo(N, PPC::SUBFIC, MVT::i32, Select(N->getOperand(1)),
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getI32Imm(Lo16(Imm)));
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return SDOperand(N, 0);
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}
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true, true)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, PPC::SUBF, MVT::i32, Select(N->getOperand(1)),
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Select(N->getOperand(0)));
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}
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return SDOperand(N, 0);
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}
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case ISD::FSUB: {
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MVT::ValueType Ty = N->getValueType(0);
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