6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-18 12:29:21 +00:00
Code Issues Projects Releases Wiki Activity

Use the autogenerated matcher for ADD/SUB

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-28 22:47:28 +00:00
parent e025574370
commit 4a7de219b4
1 changed files with 0 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -767,16 +767,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
Select(N->getOperand(0)));
return SDOperand(N, 0);
case ISD::ADD:
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
PPC::ADDIS, PPC::ADDI, true)) {
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
N = I;
} else {
CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
Select(N->getOperand(1)));
}
return SDOperand(N, 0);
case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
@ -803,26 +793,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(0)), Select(N->getOperand(1)));
return SDOperand(N, 0);
}
case ISD::SUB: {
unsigned Imm;
if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
if (0 == Imm)
CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, Select(N->getOperand(1)));
else
CurDAG->SelectNodeTo(N, PPC::SUBFIC, MVT::i32, Select(N->getOperand(1)),
getI32Imm(Lo16(Imm)));
return SDOperand(N, 0);
}
if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
PPC::ADDIS, PPC::ADDI, true, true)) {
CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
N = I;
} else {
CurDAG->SelectNodeTo(N, PPC::SUBF, MVT::i32, Select(N->getOperand(1)),
Select(N->getOperand(0)));
}
return SDOperand(N, 0);
}
case ISD::FSUB: {
MVT::ValueType Ty = N->getValueType(0);