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Use TRI::printReg instead of AbstractRegisterDescription when printing
LiveIntervalUnions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,7 +18,10 @@
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <algorithm>
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using namespace llvm;
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@ -66,24 +69,16 @@ void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
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}
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void
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LiveIntervalUnion::print(raw_ostream &OS,
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const AbstractRegisterDescription *RegDesc) const {
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LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
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OS << "LIU ";
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if (RegDesc != NULL)
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OS << RegDesc->getName(RepReg);
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else {
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OS << RepReg;
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TRI->printReg(RepReg, OS);
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for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
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OS << " [" << SI.start() << ' ' << SI.stop() << "):";
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TRI->printReg(SI.value()->reg, OS);
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}
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for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI)
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dbgs() << " [" << SI.start() << ' ' << SI.stop() << "):%reg"
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<< SI.value()->reg;
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OS << "\n";
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}
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void LiveIntervalUnion::dump(const AbstractRegisterDescription *RegDesc) const {
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print(dbgs(), RegDesc);
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}
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#ifndef NDEBUG
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// Verify the live intervals in this union and add them to the visited set.
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void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
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@ -22,19 +22,14 @@
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namespace llvm {
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class TargetRegisterInfo;
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#ifndef NDEBUG
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// forward declaration
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template <unsigned Element> class SparseBitVector;
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typedef SparseBitVector<128> LiveVirtRegBitSet;
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#endif
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/// Abstraction to provide info for the representative register.
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class AbstractRegisterDescription {
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public:
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virtual const char *getName(unsigned Reg) const = 0;
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virtual ~AbstractRegisterDescription() {}
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};
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/// Compare a live virtual register segment to a LiveIntervalUnion segment.
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inline bool
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overlap(const LiveRange &VRSeg,
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@ -85,10 +80,8 @@ public:
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// Remove a live virtual register's segments from this union.
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void extract(LiveInterval &VirtReg);
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void dump(const AbstractRegisterDescription *RegDesc) const;
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// If tri != NULL, use it to decode RepReg
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void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
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// Print union, using TRI to translate register names
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void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
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#ifndef NDEBUG
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// Verify the live intervals in this union and add them to the visited set.
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@ -60,14 +60,6 @@ VerifyRegAlloc("verify-regalloc",
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const char *RegAllocBase::TimerGroupName = "Register Allocation";
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namespace {
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class PhysicalRegisterDescription : public AbstractRegisterDescription {
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const TargetRegisterInfo *TRI;
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public:
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PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
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virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
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};
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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@ -165,8 +157,7 @@ void RegAllocBase::verify() {
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// Verify disjoint unions.
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for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
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DEBUG(PhysicalRegisterDescription PRD(TRI);
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PhysReg2LiveUnion[PhysReg].dump(&PRD));
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DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
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LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
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PhysReg2LiveUnion[PhysReg].verify(VRegs);
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// Union + intersection test could be done efficiently in one pass, but
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