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Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7123,7 +7123,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::LE);
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/*IsMinMax*/ true, ARMCC::LT);
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case ARM::ATOMMAX6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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@ -7133,7 +7133,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::LS);
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/*IsMinMax*/ true, ARMCC::LO);
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case ARM::ATOMUMAX6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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@ -133,7 +133,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: ble
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; CHECK: blt
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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@ -148,7 +148,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bls
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; CHECK: blo
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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