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Added TEST %rAX, $imm instructions to the Intel tables. These are required for the X86 disassembler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80696 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan 2009-09-01 18:14:18 +00:00
parent 17146b867f
commit 4a93b71fe7
2 changed files with 9 additions and 0 deletions
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2
lib/Target/X86/X86Instr64bit.td
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@ -984,6 +984,8 @@ def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
// Integer comparison
let Defs = [EFLAGS] in {
def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
"test{q}\t{$src, %rax|%rax, $src}", []>;
let isCommutable = 1 in
def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"test{q}\t{$src2, $src1|$src1, $src2}",

7
lib/Target/X86/X86InstrInfo.td
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@ -2753,6 +2753,13 @@ def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
(implicit EFLAGS)]>;
}
def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
"test{b}\t{$src, %al|%al, $src}", []>;
def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
"test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
"test{l}\t{$src, %eax|%eax, $src}", []>;
def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
"test{b}\t{$src2, $src1|$src1, $src2}",
[(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),