mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-05 13:26:55 +00:00
Remove the MachineMove class.
It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -636,14 +636,13 @@ void AsmPrinter::emitPrologLabel(const MachineInstr &MI) {
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OutStreamer.EmitCompactUnwindEncoding(MMI->getCompactUnwindEncoding());
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MachineModuleInfo &MMI = MF->getMMI();
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const std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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std::vector<MCCFIInstruction> Instructions = MMI.getFrameInstructions();
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bool FoundOne = false;
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(void)FoundOne;
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for (std::vector<MachineMove>::const_iterator I = Moves.begin(),
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E = Moves.end();
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I != E; ++I) {
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for (std::vector<MCCFIInstruction>::iterator I = Instructions.begin(),
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E = Instructions.end(); I != E; ++I) {
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if (I->getLabel() == Label) {
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EmitCFIFrameMove(*I);
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emitCFIInstruction(*I);
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FoundOne = true;
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}
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}
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@@ -169,28 +169,21 @@ void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
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// Dwarf Lowering Routines
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//===----------------------------------------------------------------------===//
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/// EmitCFIFrameMove - Emit a frame instruction.
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void AsmPrinter::EmitCFIFrameMove(const MachineMove &Move) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const MachineLocation &Dst = Move.getDestination();
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const MachineLocation &Src = Move.getSource();
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// If advancing cfa.
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if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
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if (Src.getReg() == MachineLocation::VirtualFP) {
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OutStreamer.EmitCFIDefCfaOffset(-Src.getOffset());
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} else {
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// Reg + Offset
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OutStreamer.EmitCFIDefCfa(RI->getDwarfRegNum(Src.getReg(), true),
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Src.getOffset());
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}
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} else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
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assert(Dst.isReg() && "Machine move not supported yet.");
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OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true));
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} else {
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assert(!Dst.isReg() && "Machine move not supported yet.");
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OutStreamer.EmitCFIOffset(RI->getDwarfRegNum(Src.getReg(), true),
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Dst.getOffset());
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void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
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switch (Inst.getOperation()) {
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default:
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llvm_unreachable("Unexpected instruction");
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case MCCFIInstruction::OpDefCfaOffset:
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OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
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break;
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case MCCFIInstruction::OpDefCfa:
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OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
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break;
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case MCCFIInstruction::OpDefCfaRegister:
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OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
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break;
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case MCCFIInstruction::OpOffset:
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OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
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break;
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}
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}
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@@ -23,7 +23,6 @@ namespace llvm {
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template <typename T> class SmallVectorImpl;
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struct LandingPadInfo;
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class MachineModuleInfo;
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class MachineMove;
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class MachineInstr;
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class MachineFunction;
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class MCAsmInfo;
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@@ -62,14 +62,8 @@ static bool getVerboseAsm() {
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llvm_unreachable("Invalid verbose asm state");
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}
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LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
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StringRef CPU, StringRef FS,
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TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: TargetMachine(T, Triple, CPU, FS, Options) {
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CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
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AsmInfo = T.createMCAsmInfo(Triple);
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void LLVMTargetMachine::initAsmInfo() {
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AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple);
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// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
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// and if the old one gets included then MCAsmInfo will be NULL and
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// we'll crash later.
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@@ -79,6 +73,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
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"and that InitializeAllTargetMCs() is being invoked!");
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}
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LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
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StringRef CPU, StringRef FS,
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TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: TargetMachine(T, Triple, CPU, FS, Options) {
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CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
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}
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void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
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}
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@@ -268,6 +268,39 @@ MachineModuleInfo::MachineModuleInfo()
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MachineModuleInfo::~MachineModuleInfo() {
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}
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static MCCFIInstruction convertMoveToCFI(const MCRegisterInfo &MRI,
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MCSymbol *Label,
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const MachineLocation &Dst,
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const MachineLocation &Src) {
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// If advancing cfa.
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if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
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if (Src.getReg() == MachineLocation::VirtualFP)
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return MCCFIInstruction::createDefCfaOffset(Label, Src.getOffset());
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// Reg + Offset
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return MCCFIInstruction::createDefCfa(
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Label, MRI.getDwarfRegNum(Src.getReg(), true), -Src.getOffset());
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}
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if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
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assert(Dst.isReg() && "Machine move not supported yet.");
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return MCCFIInstruction::createDefCfaRegister(
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Label, MRI.getDwarfRegNum(Dst.getReg(), true));
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}
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assert(!Dst.isReg() && "Machine move not supported yet.");
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return MCCFIInstruction::createOffset(
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Label, MRI.getDwarfRegNum(Src.getReg(), true), Dst.getOffset());
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}
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void MachineModuleInfo::addFrameMove(MCSymbol *Label,
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const MachineLocation &Dst,
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const MachineLocation &Src) {
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MCCFIInstruction I =
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convertMoveToCFI(Context.getRegisterInfo(), Label, Dst, Src);
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FrameInstructions.push_back(I);
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}
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bool MachineModuleInfo::doInitialization(Module &M) {
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ObjFileMMI = 0;
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@@ -303,7 +336,7 @@ bool MachineModuleInfo::doFinalization(Module &M) {
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///
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void MachineModuleInfo::EndFunction() {
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// Clean up frame info.
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FrameMoves.clear();
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FrameInstructions.clear();
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// Clean up exception info.
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LandingPads.clear();
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