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AMDGPU/SI: There are no implicit kernel args in the amdhsa ABI

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Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10706

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-06-26 21:15:03 +00:00
parent 0d1bd457c6
commit 4aad126e37
3 changed files with 10 additions and 1 deletions
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7
lib/Target/AMDGPU/AMDGPUSubtarget.h
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@ -275,6 +275,13 @@ public:
bool enableSubRegLiveness() const override {
return true;
}
/// \brief Returns the offset in bytes from the start of the input buffer
/// of the first explicit kernel argument.
unsigned getExplicitKernelArgOffset() const {
return isAmdHsaOS() ? 0 : 36;
}
};
} // End namespace llvm

3
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -583,7 +583,8 @@ SDValue SITargetLowering::LowerFormalArguments(
if (VA.isMemLoc()) {
VT = Ins[i].VT;
EVT MemVT = Splits[i].VT;
const unsigned Offset = 36 + VA.getLocMemOffset();
const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
VA.getLocMemOffset();
// The first 36 bytes of the input buffer contains information about
// thread group and global sizes.
SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),

1
test/CodeGen/AMDGPU/hsa.ll
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@ -5,6 +5,7 @@
; HSA-NEXT: .ascii "HSA Code Unit:0.0:AMD:0.1:GFX8.1:0"
; Test that the amd_kernel_code_t object is emitted
; HSA: .asciz
; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0
; Make sure we are setting the ATC bit:
; HSA: s_mov_b32 s[[HI:[0-9]]], 0x100f000
; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0