mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
64437ead05
commit
4aee1bb222
@ -77,9 +77,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
|
||||
case X86::VPALIGNR128rm:
|
||||
Src2Name = getRegName(MI->getOperand(1).getReg());
|
||||
DestName = getRegName(MI->getOperand(0).getReg());
|
||||
DecodePALIGNMask(MVT::v16i8,
|
||||
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
||||
ShuffleMask);
|
||||
DecodePALIGNRMask(MVT::v16i8,
|
||||
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
||||
ShuffleMask);
|
||||
break;
|
||||
case X86::VPALIGNR256rr:
|
||||
Src1Name = getRegName(MI->getOperand(2).getReg());
|
||||
@ -87,9 +87,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
|
||||
case X86::VPALIGNR256rm:
|
||||
Src2Name = getRegName(MI->getOperand(1).getReg());
|
||||
DestName = getRegName(MI->getOperand(0).getReg());
|
||||
DecodePALIGNMask(MVT::v32i8,
|
||||
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
||||
ShuffleMask);
|
||||
DecodePALIGNRMask(MVT::v32i8,
|
||||
MI->getOperand(MI->getNumOperands()-1).getImm(),
|
||||
ShuffleMask);
|
||||
|
||||
case X86::PSHUFDri:
|
||||
case X86::VPSHUFDri:
|
||||
|
||||
@ -61,7 +61,8 @@ void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
|
||||
ShuffleMask.push_back(NElts+i);
|
||||
}
|
||||
|
||||
void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
|
||||
void DecodePALIGNRMask(MVT VT, unsigned Imm,
|
||||
SmallVectorImpl<int> &ShuffleMask) {
|
||||
unsigned NumElts = VT.getVectorNumElements();
|
||||
unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
|
||||
|
||||
|
||||
@ -35,7 +35,7 @@ void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
|
||||
// <0,2> or <0,1,4,5>
|
||||
void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
|
||||
|
||||
void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
|
||||
void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
|
||||
|
||||
void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
|
||||
|
||||
|
||||
@ -3004,7 +3004,7 @@ static bool isTargetShuffle(unsigned Opcode) {
|
||||
case X86ISD::PSHUFHW:
|
||||
case X86ISD::PSHUFLW:
|
||||
case X86ISD::SHUFP:
|
||||
case X86ISD::PALIGN:
|
||||
case X86ISD::PALIGNR:
|
||||
case X86ISD::MOVLHPS:
|
||||
case X86ISD::MOVLHPD:
|
||||
case X86ISD::MOVHLPS:
|
||||
@ -3054,7 +3054,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
|
||||
SelectionDAG &DAG) {
|
||||
switch(Opc) {
|
||||
default: llvm_unreachable("Unknown x86 shuffle node");
|
||||
case X86ISD::PALIGN:
|
||||
case X86ISD::PALIGNR:
|
||||
case X86ISD::SHUFP:
|
||||
case X86ISD::VPERM2X128:
|
||||
return DAG.getNode(Opc, dl, VT, V1, V2,
|
||||
@ -4592,9 +4592,9 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT,
|
||||
case X86ISD::MOVLHPS:
|
||||
DecodeMOVLHPSMask(NumElems, Mask);
|
||||
break;
|
||||
case X86ISD::PALIGN:
|
||||
case X86ISD::PALIGNR:
|
||||
ImmN = N->getOperand(N->getNumOperands()-1);
|
||||
DecodePALIGNMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
|
||||
DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
|
||||
break;
|
||||
case X86ISD::PSHUFD:
|
||||
case X86ISD::VPERMILP:
|
||||
@ -6932,7 +6932,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
|
||||
// nodes, and remove one by one until they don't return Op anymore.
|
||||
|
||||
if (isPALIGNRMask(M, VT, Subtarget))
|
||||
return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
|
||||
return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
|
||||
getShufflePALIGNRImmediate(SVOp),
|
||||
DAG);
|
||||
|
||||
@ -12435,7 +12435,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
|
||||
case X86ISD::PTEST: return "X86ISD::PTEST";
|
||||
case X86ISD::TESTP: return "X86ISD::TESTP";
|
||||
case X86ISD::PALIGN: return "X86ISD::PALIGN";
|
||||
case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
|
||||
case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
|
||||
case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
|
||||
case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
|
||||
@ -17416,7 +17416,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
|
||||
case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
|
||||
case X86ISD::SHUFP: // Handle all target specific shuffles
|
||||
case X86ISD::PALIGN:
|
||||
case X86ISD::PALIGNR:
|
||||
case X86ISD::UNPCKH:
|
||||
case X86ISD::UNPCKL:
|
||||
case X86ISD::MOVHLPS:
|
||||
|
||||
@ -294,7 +294,7 @@ namespace llvm {
|
||||
TESTP,
|
||||
|
||||
// Several flavors of instructions with vector shuffle behaviors.
|
||||
PALIGN,
|
||||
PALIGNR,
|
||||
PSHUFD,
|
||||
PSHUFHW,
|
||||
PSHUFLW,
|
||||
|
||||
@ -160,7 +160,7 @@ def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
|
||||
def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
|
||||
|
||||
def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
|
||||
def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
|
||||
|
||||
def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
|
||||
def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
|
||||
|
||||
@ -5167,7 +5167,7 @@ defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
|
||||
// SSSE3 - Packed Align Instruction Patterns
|
||||
//===---------------------------------------------------------------------===//
|
||||
|
||||
multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
|
||||
multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
|
||||
let neverHasSideEffects = 1 in {
|
||||
def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
@ -5187,7 +5187,7 @@ multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
|
||||
}
|
||||
}
|
||||
|
||||
multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
|
||||
multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
|
||||
let neverHasSideEffects = 1 in {
|
||||
def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, i8imm:$src3),
|
||||
@ -5204,42 +5204,42 @@ multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX] in
|
||||
defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
|
||||
defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
|
||||
let Predicates = [HasAVX2] in
|
||||
defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
|
||||
defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
|
||||
let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
|
||||
defm PALIGN : ssse3_palign<"palignr">;
|
||||
defm PALIGN : ssse3_palignr<"palignr">;
|
||||
|
||||
let Predicates = [HasAVX2] in {
|
||||
def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
|
||||
def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
|
||||
def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
|
||||
def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX] in {
|
||||
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
}
|
||||
|
||||
let Predicates = [UseSSSE3] in {
|
||||
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user