mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 00:32:55 +00:00
Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
64437ead05
commit
4aee1bb222
@ -77,9 +77,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::VPALIGNR128rm:
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Src2Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePALIGNMask(MVT::v16i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodePALIGNRMask(MVT::v16i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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case X86::VPALIGNR256rr:
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Src1Name = getRegName(MI->getOperand(2).getReg());
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@ -87,9 +87,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::VPALIGNR256rm:
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Src2Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePALIGNMask(MVT::v32i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodePALIGNRMask(MVT::v32i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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case X86::PSHUFDri:
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case X86::VPSHUFDri:
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@ -61,7 +61,8 @@ void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask) {
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ShuffleMask.push_back(NElts+i);
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}
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void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
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void DecodePALIGNRMask(MVT VT, unsigned Imm,
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SmallVectorImpl<int> &ShuffleMask) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
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@ -35,7 +35,7 @@ void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
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// <0,2> or <0,1,4,5>
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void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
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void DecodePALIGNMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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@ -3004,7 +3004,7 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::PSHUFHW:
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case X86ISD::PSHUFLW:
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case X86ISD::SHUFP:
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case X86ISD::PALIGN:
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case X86ISD::PALIGNR:
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case X86ISD::MOVLHPS:
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case X86ISD::MOVLHPD:
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case X86ISD::MOVHLPS:
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@ -3054,7 +3054,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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SelectionDAG &DAG) {
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switch(Opc) {
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default: llvm_unreachable("Unknown x86 shuffle node");
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case X86ISD::PALIGN:
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case X86ISD::PALIGNR:
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case X86ISD::SHUFP:
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case X86ISD::VPERM2X128:
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return DAG.getNode(Opc, dl, VT, V1, V2,
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@ -4592,9 +4592,9 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT,
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case X86ISD::MOVLHPS:
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DecodeMOVLHPSMask(NumElems, Mask);
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break;
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case X86ISD::PALIGN:
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case X86ISD::PALIGNR:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodePALIGNMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
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DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
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break;
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case X86ISD::PSHUFD:
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case X86ISD::VPERMILP:
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@ -6932,7 +6932,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// nodes, and remove one by one until they don't return Op anymore.
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if (isPALIGNRMask(M, VT, Subtarget))
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return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
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return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
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getShufflePALIGNRImmediate(SVOp),
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DAG);
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@ -12435,7 +12435,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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case X86ISD::PTEST: return "X86ISD::PTEST";
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case X86ISD::TESTP: return "X86ISD::TESTP";
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case X86ISD::PALIGN: return "X86ISD::PALIGN";
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case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
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case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
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case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
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case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
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@ -17416,7 +17416,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
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case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
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case X86ISD::SHUFP: // Handle all target specific shuffles
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case X86ISD::PALIGN:
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case X86ISD::PALIGNR:
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case X86ISD::UNPCKH:
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case X86ISD::UNPCKL:
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case X86ISD::MOVHLPS:
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@ -294,7 +294,7 @@ namespace llvm {
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TESTP,
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// Several flavors of instructions with vector shuffle behaviors.
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PALIGN,
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PALIGNR,
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PSHUFD,
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PSHUFHW,
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PSHUFLW,
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@ -160,7 +160,7 @@ def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
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SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
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def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
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def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
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def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
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def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
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@ -5167,7 +5167,7 @@ defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
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// SSSE3 - Packed Align Instruction Patterns
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//===---------------------------------------------------------------------===//
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multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
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multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
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let neverHasSideEffects = 1 in {
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def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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@ -5187,7 +5187,7 @@ multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
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}
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}
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multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
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multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
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let neverHasSideEffects = 1 in {
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def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, i8imm:$src3),
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@ -5204,42 +5204,42 @@ multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
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}
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let Predicates = [HasAVX] in
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defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
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defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
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let Predicates = [HasAVX2] in
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defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
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defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
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defm PALIGN : ssse3_palign<"palignr">;
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defm PALIGN : ssse3_palignr<"palignr">;
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let Predicates = [HasAVX2] in {
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def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
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def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
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def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
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def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
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(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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}
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let Predicates = [UseSSSE3] in {
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def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
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}
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