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https://github.com/c64scene-ar/llvm-6502.git
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Fix newly-introduced 4.3 warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47375 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -34,7 +34,7 @@ namespace llvm {
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getCalleeSaveSpillSlots(unsigned &NumEntries) const;
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//! Stack slot size (16 bytes)
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static const int stackSlotSize() {
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static int stackSlotSize() {
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return 16;
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}
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//! Maximum frame offset representable by a signed 10-bit integer
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@@ -42,19 +42,19 @@ namespace llvm {
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This is the maximum frame offset that can be expressed as a 10-bit
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integer, used in D-form addresses.
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*/
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static const int maxFrameOffset() {
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static int maxFrameOffset() {
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return ((1 << 9) - 1) * stackSlotSize();
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}
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//! Minimum frame offset representable by a signed 10-bit integer
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static const int minFrameOffset() {
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static int minFrameOffset() {
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return -(1 << 9) * stackSlotSize();
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}
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//! Minimum frame size (enough to spill LR + SP)
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static const int minStackSize() {
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static int minStackSize() {
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return (2 * stackSlotSize());
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}
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//! Frame size required to spill all registers plus frame info
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static const int fullSpillSize() {
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static int fullSpillSize() {
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return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
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}
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//! Number of instructions required to overcome hint-for-branch latency
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@@ -65,7 +65,7 @@ namespace llvm {
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of instructions occurs between the HBR and the target. Currently, HBRs
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take 6 cycles, ergo, the magic number 6.
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*/
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static const int branchHintPenalty() {
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static int branchHintPenalty() {
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return 6;
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}
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};
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