6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 04:56:49 +00:00
Code Issues Projects Releases Wiki Activity

Revert "Don't check liveness of unallocatable registers."

Browse Source 
The ARM target depends on CPSR liveness being tracked after register
allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-07-30 00:57:25 +00:00
parent 2e1513d9cd
commit 4af0f5fecb
3 changed files with 5 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/CodeGen/MachineVerifier.cpp
View File

@ -664,15 +664,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Use of a dead register.
if (!regsLive.count(Reg)) {
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
// Reserved registers may be used even when 'dead', but allocatable
// registers can't.
// We track the liveness of unreserved, unallocatable registers while
// the machine function is still in SSA form. That lets us check for
// bad EFLAGS uses. After register allocation, the unallocatable
// registers are probably quite wrong. For example, the x87 ST0-ST7
// registers don't track liveness at all.
if (!isReserved(Reg) &&
(MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
// Reserved registers may be used even when 'dead'.
if (!isReserved(Reg))
report("Using an undefined physical register", MO, MONum);
} else {
BBInfo &MInfo = MBBInfoMap[MI->getParent()];

4
lib/CodeGen/RegisterScavenging.cpp
View File

@ -157,7 +157,7 @@ void RegScavenger::forward() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
if (!Reg || isReserved(Reg))
continue;
if (MO.isUse()) {
@ -184,7 +184,7 @@ void RegScavenger::forward() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
if (!Reg || isReserved(Reg))
continue;
if (MO.isUse()) {
if (MO.isUndef())

2
test/CodeGen/X86/vector.ll
View File

@ -1,6 +1,6 @@
; Test that vectors are scalarized/lowered correctly.
; RUN: llc < %s -march=x86 -mcpu=i386 > %t
; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
%d8 = type <8 x double>
%f1 = type <1 x float>