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Rename parameter: defined regs are not incoming.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192391 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
2013-10-10 21:28:38 +00:00
parent 4d91232df1
commit 4afb5f560d
2 changed files with 17 additions and 18 deletions
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5
include/llvm/CodeGen/MachineInstr.h
View File

@ -893,13 +893,12 @@ public:
/// Look for the operand that defines it and mark it as IsDead. If /// Look for the operand that defines it and mark it as IsDead. If
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
/// true if the operand exists / is added. /// true if the operand exists / is added.
bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
bool AddIfNotFound = false); bool AddIfNotFound = false);
/// addRegisterDefined - We have determined MI defines a register. Make sure /// addRegisterDefined - We have determined MI defines a register. Make sure
/// there is an operand defining Reg. /// there is an operand defining Reg.
void addRegisterDefined(unsigned IncomingReg, void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo = 0);
const TargetRegisterInfo *RegInfo = 0);
/// setPhysRegsDeadExcept - Mark every physreg used by this instruction as /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
/// dead except those in the UsedRegs list. /// dead except those in the UsedRegs list.

30
lib/CodeGen/MachineInstr.cpp
View File

@ -1702,31 +1702,31 @@ void MachineInstr::clearRegisterKills(unsigned Reg,
} }
} }
bool MachineInstr::addRegisterDead(unsigned IncomingReg, bool MachineInstr::addRegisterDead(unsigned Reg,
const TargetRegisterInfo *RegInfo, const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) { bool AddIfNotFound) {
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
bool hasAliases = isPhysReg && bool hasAliases = isPhysReg &&
MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); MCRegAliasIterator(Reg, RegInfo, false).isValid();
bool Found = false; bool Found = false;
SmallVector<unsigned,4> DeadOps; SmallVector<unsigned,4> DeadOps;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i); MachineOperand &MO = getOperand(i);
if (!MO.isReg() || !MO.isDef()) if (!MO.isReg() || !MO.isDef())
continue; continue;
unsigned Reg = MO.getReg(); unsigned MOReg = MO.getReg();
if (!Reg) if (!MOReg)
continue; continue;
if (Reg == IncomingReg) { if (MOReg == Reg) {
MO.setIsDead(); MO.setIsDead();
Found = true; Found = true;
} else if (hasAliases && MO.isDead() && } else if (hasAliases && MO.isDead() &&
TargetRegisterInfo::isPhysicalRegister(Reg)) { TargetRegisterInfo::isPhysicalRegister(MOReg)) {
// There exists a super-register that's marked dead. // There exists a super-register that's marked dead.
if (RegInfo->isSuperRegister(IncomingReg, Reg)) if (RegInfo->isSuperRegister(Reg, MOReg))
return true; return true;
if (RegInfo->isSubRegister(IncomingReg, Reg)) if (RegInfo->isSubRegister(Reg, MOReg))
DeadOps.push_back(i); DeadOps.push_back(i);
} }
} }
@ -1746,7 +1746,7 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
if (Found || !AddIfNotFound) if (Found || !AddIfNotFound)
return Found; return Found;
addOperand(MachineOperand::CreateReg(IncomingReg, addOperand(MachineOperand::CreateReg(Reg,
true /*IsDef*/, true /*IsDef*/,
true /*IsImp*/, true /*IsImp*/,
false /*IsKill*/, false /*IsKill*/,
@ -1754,21 +1754,21 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg,
return true; return true;
} }
void MachineInstr::addRegisterDefined(unsigned IncomingReg, void MachineInstr::addRegisterDefined(unsigned Reg,
const TargetRegisterInfo *RegInfo) { const TargetRegisterInfo *RegInfo) {
if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
if (MO) if (MO)
return; return;
} else { } else {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i); const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
MO.getSubReg() == 0) MO.getSubReg() == 0)
return; return;
} }
} }
addOperand(MachineOperand::CreateReg(IncomingReg, addOperand(MachineOperand::CreateReg(Reg,
true /*IsDef*/, true /*IsDef*/,
true /*IsImp*/)); true /*IsImp*/));
} }