From 4b2a174e21b7cfc2c45db895efc7c638e4c68538 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 18 Jun 2011 02:30:02 +0000 Subject: [PATCH] Delete unneeded allocation order override. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133331 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Blackfin/BlackfinRegisterInfo.td | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index 9e2f79f3849..0d502fdcc7e 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -254,17 +254,7 @@ def PI : RegisterClass<"BF", [i32], 32, (add P, I)>; let CopyCost = -1, Size = 8 in { def JustCC : RegisterClass<"BF", [i32], 8, (add CC)>; def NotCC : RegisterClass<"BF", [i32], 8, (add NCC)>; -def AnyCC : RegisterClass<"BF", [i32], 8, (add CC, NCC)> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - AnyCCClass::iterator - AnyCCClass::allocation_order_end(const MachineFunction &MF) const { - return allocation_order_begin(MF)+1; - } - }]; -} +def AnyCC : RegisterClass<"BF", [i32], 8, (add CC, NCC)>; def StatBit : RegisterClass<"BF", [i1], 8, (add AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS)>; }