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[FastISel][AArch64] Followup commit for 218031 to handle negative offsets too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218032 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -917,11 +917,15 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
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// Since the offset is too large for the load/store instruction get the
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// reg+offset into a register.
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if (ImmediateOffsetNeedsLowering) {
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unsigned ResultReg = 0;
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unsigned ResultReg;
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if (Addr.getReg()) {
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// Try to fold the immediate into the add instruction.
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ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
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/*IsKill=*/false, Offset);
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if (Offset < 0)
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ResultReg = emitAddSub_ri(/*UseAdd=*/false, MVT::i64, Addr.getReg(),
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/*IsKill=*/false, -Offset);
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else
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ResultReg = emitAddSub_ri(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
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/*IsKill=*/false, Offset);
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if (!ResultReg) {
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unsigned ImmReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
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ResultReg = emitAddSub_rr(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
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@ -130,12 +130,9 @@ define i32 @load_breg_immoff_1(i64 %a) {
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; Min not-supported negative offset
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define i32 @load_breg_immoff_2(i64 %a) {
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; SDAG-LABEL: load_breg_immoff_2
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; SDAG: sub [[REG:x[0-9]+]], x0, #257
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; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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; FAST-LABEL: load_breg_immoff_2
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; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
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; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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; CHECK-LABEL: load_breg_immoff_2
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; CHECK: sub [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, -257
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%2 = inttoptr i64 %1 to i32*
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%3 = load i32* %2
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@ -196,12 +193,9 @@ define void @store_breg_immoff_1(i64 %a) {
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; Min not-supported negative offset
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define void @store_breg_immoff_2(i64 %a) {
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; SDAG-LABEL: store_breg_immoff_2
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; SDAG: sub [[REG:x[0-9]+]], x0, #257
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; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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; FAST-LABEL: store_breg_immoff_2
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; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
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; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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; CHECK-LABEL: store_breg_immoff_2
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; CHECK: sub [[REG:x[0-9]+]], x0, #257
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; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, -257
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%2 = inttoptr i64 %1 to i32*
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store i32 0, i32* %2
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