mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available. rdar://7956878 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ed66bf5125
commit
4b77f6a85a
@ -393,8 +393,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
|
||||
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
|
||||
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
|
||||
|
||||
if (!Subtarget->hasV6Ops() && (!Subtarget->isThumb2()
|
||||
|| !Subtarget->hasT2ExtractPack())) {
|
||||
// If the subtarget does not have extract instructions, sign_extend_inreg
|
||||
// needs to be expanded. Extract is available in ARM mode on v6 and up,
|
||||
// and on most Thumb2 implementations.
|
||||
if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops())
|
||||
|| (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
|
||||
}
|
||||
|
22
test/CodeGen/Thumb2/sign_extend_inreg.ll
Normal file
22
test/CodeGen/Thumb2/sign_extend_inreg.ll
Normal file
@ -0,0 +1,22 @@
|
||||
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8
|
||||
; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3
|
||||
|
||||
target triple = "thumbv7-apple-darwin10"
|
||||
|
||||
define arm_apcscc i32 @f1(i16* %ptr) nounwind {
|
||||
; CHECK-A8: f1
|
||||
; CHECK-A8: sxth
|
||||
; CHECK-M3: f1
|
||||
; CHECK-M3-NOT: sxth
|
||||
; CHECK-M3: bx lr
|
||||
%1 = load i16* %ptr
|
||||
%2 = icmp eq i16 %1, 1
|
||||
%3 = sext i16 %1 to i32
|
||||
br i1 %2, label %.next, label %.exit
|
||||
|
||||
.next:
|
||||
br label %.exit
|
||||
|
||||
.exit:
|
||||
ret i32 %3
|
||||
}
|
Loading…
Reference in New Issue
Block a user