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ARM disassembler did not react to recent changes to the NEON instruction table.

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VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-04-19 16:20:34 +00:00
parent 9d44e70272
commit 4b7df442a8
2 changed files with 26 additions and 10 deletions
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32
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2232,6 +2232,22 @@ static unsigned decodeN3VImm(uint32_t insn) {
return (insn >> 8) & 0xF;
}
static bool UseDRegPair(unsigned Opcode) {
switch (Opcode) {
default:
return false;
case ARM::VLD1q8_UPD:
case ARM::VLD1q16_UPD:
case ARM::VLD1q32_UPD:
case ARM::VLD1q64_UPD:
case ARM::VST1q8_UPD:
case ARM::VST1q16_UPD:
case ARM::VST1q32_UPD:
case ARM::VST1q64_UPD:
return true;
}
}
// VLD*
// D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
// VLD*LN*
@ -2305,11 +2321,9 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
RegClass = OpInfo[OpIdx].RegClass;
while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
if (Opcode >= ARM::VST1q16 && Opcode <= ARM::VST1q8)
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
true)));
else
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,Rd)));
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
Rd += Inc;
++OpIdx;
}
@ -2327,11 +2341,9 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
RegClass = OpInfo[0].RegClass;
while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
if (Opcode >= ARM::VLD1q16 && Opcode <= ARM::VLD1q8)
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd,
true)));
else
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass, Rd)));
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
Rd += Inc;
++OpIdx;
}

4
test/MC/Disassembler/neon-tests.txt
View File

@ -9,6 +9,10 @@
# CHECK: vdup.32 q3, d1[0]
0x41 0x6c 0xb4 0xf3
# VLD1q8_UPD (with ${dst:dregpair} operand)
# CHECK: vld1.8 {d17, d18}, [r6], r5
0x05 0x1a 0x66 0xf4
# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7
0x07 0x00 0x22 0xf4