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Get the register and count from the register list operands.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-08 23:51:20 +00:00
parent 3734ef3fb4
commit 4b97c55648
1 changed files with 5 additions and 8 deletions
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13
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -378,14 +378,11 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op, getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &) const {
// Convert a list of GPRs into a bitfield (R0 -> bit 0). For each // {12-8} = Rd
// register in the list, set the corresponding bit. // {7-0} = count
unsigned Binary = 0; unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) { Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
Binary |= 1 << regno;
}
return Binary; return Binary;
} }