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Fix PR1316

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35783 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-04-09 00:33:58 +00:00
parent 8dd4f533c8
commit 4b993b19f9
1 changed files with 4 additions and 4 deletions
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8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -2439,8 +2439,6 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
}
case Intrinsic::bit_part_select: {
// MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
// setValue(&I, DAG.getTargetConstant(0, Ty));
// Currently not implemented: just abort
assert(0 && "bit_part_select intrinsic not implemented");
abort();
@ -2687,7 +2685,8 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
/// values added into it.
void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
std::vector<SDOperand> &Ops) const {
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), MVT::i32));
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
Ops.push_back(DAG.getRegister(Regs[i], RegVT));
}
@ -4524,8 +4523,9 @@ SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
}
// Add this to the output node.
MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
MVT::i32));
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;
}