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ARM IAS: account for predicated pre-UAL mnemonics

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Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2013-12-30 18:38:01 +00:00
parent 98b356bc64
commit 4ba4132d62
3 changed files with 52 additions and 7 deletions
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33
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -5107,18 +5107,37 @@ static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
} }
static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
unsigned VariantID); unsigned VariantID);
static bool RequiresVFPRegListValidation(StringRef Inst,
bool &AcceptSinglePrecisionOnly,
bool &AcceptDoublePrecisionOnly) {
if (Inst.size() < 7)
return false;
if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
StringRef AddressingMode = Inst.substr(4, 2);
if (AddressingMode == "ia" || AddressingMode == "db" ||
AddressingMode == "ea" || AddressingMode == "fd") {
AcceptSinglePrecisionOnly = Inst[6] == 's';
AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
return true;
}
}
return false;
}
/// Parse an arm instruction mnemonic followed by its operands. /// Parse an arm instruction mnemonic followed by its operands.
bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) { SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// FIXME: Can this be done via tablegen in some fashion? // FIXME: Can this be done via tablegen in some fashion?
bool RequireVFPRegisterList; bool RequireVFPRegisterListCheck;
bool AcceptDoublePrecisionOnly;
bool AcceptSinglePrecisionOnly; bool AcceptSinglePrecisionOnly;
RequireVFPRegisterList = Name.startswith("fldm") || Name.startswith("fstm"); bool AcceptDoublePrecisionOnly;
AcceptDoublePrecisionOnly = RequireVFPRegisterListCheck =
RequireVFPRegisterList && (Name.back() == 'd' || Name.back() == 'x'); RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
AcceptSinglePrecisionOnly = RequireVFPRegisterList && Name.back() == 's'; AcceptDoublePrecisionOnly);
// Apply mnemonic aliases before doing anything else, as the destination // Apply mnemonic aliases before doing anything else, as the destination
// mnemonic may include suffices and we want to handle them normally. // mnemonic may include suffices and we want to handle them normally.
@ -5288,7 +5307,7 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
Parser.Lex(); // Consume the EndOfStatement Parser.Lex(); // Consume the EndOfStatement
if (RequireVFPRegisterList) { if (RequireVFPRegisterListCheck) {
ARMOperand *Op = static_cast<ARMOperand*>(Operands.back()); ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
if (AcceptSinglePrecisionOnly && !Op->isSPRRegList()) if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
return Error(Op->getStartLoc(), return Error(Op->getStartLoc(),

17
test/MC/ARM/vfp-aliases-diagnostics.s
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@ -95,3 +95,20 @@ aliases:
@ CHECK: fldmeax sp!, {s0} @ CHECK: fldmeax sp!, {s0}
@ CHECK: ^ @ CHECK: ^
fstmiaxcs r0, {s0}
fstmiaxhs r0, {s0}
fstmiaxls r0, {s0}
fstmiaxvs r0, {s0}
@ CHECK: error: VFP/Neon double precision register expected
@ CHECK: fstmiaxcs r0, {s0}
@ CHECK: ^
@ CHECK: error: VFP/Neon double precision register expected
@ CHECK: fstmiaxhs r0, {s0}
@ CHECK: ^
@ CHECK: error: VFP/Neon double precision register expected
@ CHECK: fstmiaxls r0, {s0}
@ CHECK: ^
@ CHECK: error: VFP/Neon double precision register expected
@ CHECK: fstmiaxvs r0, {s0}
@ CHECK: ^

9
test/MC/ARM/vfp-aliases.s
View File

@ -51,3 +51,12 @@ aliases:
@ CHECK: fstmdbx sp!, {d0} @ CHECK: fstmdbx sp!, {d0}
@ CHECK: fldmdbx sp!, {d0} @ CHECK: fldmdbx sp!, {d0}
fstmiaxcs r0, {d0}
fstmiaxhs r0, {d0}
fstmiaxls r0, {d0}
fstmiaxvs r0, {d0}
@ CHECK: fstmiaxhs r0, {d0}
@ CHECK: fstmiaxhs r0, {d0}
@ CHECK: fstmiaxls r0, {d0}
@ CHECK: fstmiaxvs r0, {d0}