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Save/restore VRSAVE once per function, not once per block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,17 +39,21 @@ namespace {
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/// instructions for SelectionDAG operations.
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///
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class PPCDAGToDAGISel : public SelectionDAGISel {
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PPCTargetMachine &TM;
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PPCTargetLowering PPCLowering;
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unsigned GlobalBaseReg;
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public:
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PPCDAGToDAGISel(PPCTargetMachine &TM)
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: SelectionDAGISel(PPCLowering),
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PPCLowering(*TM.getTargetLowering()){}
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PPCDAGToDAGISel(PPCTargetMachine &tm)
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: SelectionDAGISel(PPCLowering), TM(tm),
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PPCLowering(*TM.getTargetLowering()) {}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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SelectionDAGISel::runOnFunction(Fn);
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InsertVRSaveCode(Fn);
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return true;
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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@ -121,6 +125,8 @@ namespace {
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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void InsertVRSaveCode(Function &Fn);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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@ -199,13 +205,19 @@ void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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/// InsertVRSaveCode - Once the entire function has been instruction selected,
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/// all virtual registers are created and all machine instructions are built,
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/// check to see if we need to save/restore VRSAVE. If so, do it.
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void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
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// Check to see if this function uses vector registers, which means we have to
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// save and restore the VRSAVE register and update it with the regs we use.
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//
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// In this case, there will be virtual registers of vector type type created
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// by the scheduler. Detect them now.
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SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
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MachineFunction &Fn = MachineFunction::get(&F);
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SSARegMap *RegMap = Fn.getSSARegMap();
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bool HasVectorVReg = false;
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = RegMap->getLastVirtReg()+1; i != e; ++i)
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@ -213,7 +225,8 @@ void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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HasVectorVReg = true;
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break;
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}
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if (!HasVectorVReg) return; // nothing to do.
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// If we have a vector register, we want to emit code into the entry and exit
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// blocks to save and restore the VRSAVE register. We do this here (instead
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// of marking all vector instructions as clobbering VRSAVE) for two reasons:
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@ -223,41 +236,41 @@ void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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// 2. This (more significantly) allows us to create a temporary virtual
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// register to hold the saved VRSAVE value, allowing this temporary to be
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// register allocated, instead of forcing it to be spilled to the stack.
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if (HasVectorVReg) {
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// Create two vregs - one to hold the VRSAVE register that is live-in to the
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// function and one for the value after having bits or'd into it.
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unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MachineFunction &MF = DAG.getMachineFunction();
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MachineBasicBlock &EntryBB = *MF.begin();
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// Emit the following code into the entry block:
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// InVRSAVE = MFVRSAVE
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// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
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// MTVRSAVE UpdatedVRSAVE
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MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
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BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
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BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
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BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
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// Find all return blocks, outputting a restore in each epilog.
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const TargetInstrInfo &TII = *DAG.getTarget().getInstrInfo();
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
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IP = BB->end(); --IP;
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// Skip over all terminator instructions, which are part of the return
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// sequence.
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MachineBasicBlock::iterator I2 = IP;
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while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
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IP = I2;
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// Emit: MTVRSAVE InVRSave
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BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
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}
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// Create two vregs - one to hold the VRSAVE register that is live-in to the
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// function and one for the value after having bits or'd into it.
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unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MachineBasicBlock &EntryBB = *Fn.begin();
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// Emit the following code into the entry block:
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// InVRSAVE = MFVRSAVE
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// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
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// MTVRSAVE UpdatedVRSAVE
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MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
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BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
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BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
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BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
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// Find all return blocks, outputting a restore in each epilog.
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
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if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
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IP = BB->end(); --IP;
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// Skip over all terminator instructions, which are part of the return
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// sequence.
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MachineBasicBlock::iterator I2 = IP;
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while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
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IP = I2;
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// Emit: MTVRSAVE InVRSave
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BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
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}
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}
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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