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Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can now

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scan the register file for sub- and super-registers.
No functionality change intended.

(Tests are updated because the comments in the assembler output are
different.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202416 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adrian Prantl
2014-02-27 17:56:08 +00:00
parent cc331c8f40
commit 4bd26ae070
7 changed files with 101 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/ARM/ARMAsmPrinter.cpp
-64
View File
@@ -55,70 +55,6 @@
#include <cctype>
using namespace llvm;
/// EmitDwarfRegOp - Emit dwarf register operation.
void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
bool Indirect) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
return;
}
assert(MLoc.isReg() && !Indirect &&
"This doesn't support offset/indirection - implement it if needed");
unsigned Reg = MLoc.getReg();
if (Reg >= ARM::S0 && Reg <= ARM::S31) {
assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
// S registers are described as bit-pieces of a register
// S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
// S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
unsigned SReg = Reg - ARM::S0;
bool odd = SReg & 0x1;
unsigned Rx = 256 + (SReg >> 1);
OutStreamer.AddComment("DW_OP_regx for S register");
EmitInt8(dwarf::DW_OP_regx);
OutStreamer.AddComment(Twine(SReg));
EmitULEB128(Rx);
if (odd) {
OutStreamer.AddComment("DW_OP_bit_piece 32 32");
EmitInt8(dwarf::DW_OP_bit_piece);
EmitULEB128(32);
EmitULEB128(32);
} else {
OutStreamer.AddComment("DW_OP_bit_piece 32 0");
EmitInt8(dwarf::DW_OP_bit_piece);
EmitULEB128(32);
EmitULEB128(0);
}
} else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
// Q registers Q0-Q15 are described by composing two D registers together.
// Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
// DW_OP_piece(8)
unsigned QReg = Reg - ARM::Q0;
unsigned D1 = 256 + 2 * QReg;
unsigned D2 = D1 + 1;
OutStreamer.AddComment("DW_OP_regx for Q register: D1");
EmitInt8(dwarf::DW_OP_regx);
EmitULEB128(D1);
OutStreamer.AddComment("DW_OP_piece 8");
EmitInt8(dwarf::DW_OP_piece);
EmitULEB128(8);
OutStreamer.AddComment("DW_OP_regx for Q register: D2");
EmitInt8(dwarf::DW_OP_regx);
EmitULEB128(D2);
OutStreamer.AddComment("DW_OP_piece 8");
EmitInt8(dwarf::DW_OP_piece);
EmitULEB128(8);
}
}
void ARMAsmPrinter::EmitFunctionBodyEnd() {
// Make sure to terminate any constant pools that were at the end
// of the function.