mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-05-28 00:40:54 +00:00
Add support for shift instructions, wrap some long lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12740 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
a562efce35
commit
4be7ca5721
@ -57,9 +57,10 @@ namespace {
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BB = MBBMap[&LLVM_BB];
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BB = MBBMap[&LLVM_BB];
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}
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}
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void visitBinaryOperator(BinaryOperator &I);
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void visitBinaryOperator(Instruction &I);
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void visitCallInst(CallInst &I);
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void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
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void visitReturnInst(ReturnInst &RI);
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void visitCallInst(CallInst &I);
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void visitReturnInst(ReturnInst &RI);
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void visitInstruction(Instruction &I) {
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void visitInstruction(Instruction &I) {
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std::cerr << "Unhandled instruction: " << I;
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std::cerr << "Unhandled instruction: " << I;
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@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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unsigned Class = getClass(C->getType());
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unsigned Class = getClass(C->getType());
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uint64_t Val = CI->getRawValue ();
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switch (Class) {
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switch (Class) {
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case cByte:
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
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return;
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return;
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case cShort: {
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case cShort: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
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.addImm (((uint16_t) Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint16_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cInt: {
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case cInt: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint32_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cLong: {
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case cLong: {
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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uint32_t topHalf, bottomHalf;
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uint32_t topHalf = (uint32_t) (Val >> 32);
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topHalf = (uint32_t) (CI->getRawValue () >> 32);
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uint32_t bottomHalf = (uint32_t)Val;
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bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (bottomHalf & 0x03ff);
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return;
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return;
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}
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}
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default:
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default:
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@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
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return;
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return;
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}
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}
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void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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void V8ISel::visitBinaryOperator (Instruction &I) {
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unsigned DestReg = getReg (I);
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned Op1Reg = getReg (I.getOperand (1));
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@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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case Instruction::And: OpCase = 3; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Shl: OpCase = 6; break;
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case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
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case Instruction::Div:
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case Instruction::Div:
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case Instruction::Rem: {
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case Instruction::Rem: {
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@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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if (OpCase != ~0U) {
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
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V8::SLLrr, V8::SRLrr, V8::SRArr
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};
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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}
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@ -57,9 +57,10 @@ namespace {
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BB = MBBMap[&LLVM_BB];
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BB = MBBMap[&LLVM_BB];
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}
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}
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void visitBinaryOperator(BinaryOperator &I);
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void visitBinaryOperator(Instruction &I);
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void visitCallInst(CallInst &I);
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void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
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void visitReturnInst(ReturnInst &RI);
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void visitCallInst(CallInst &I);
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void visitReturnInst(ReturnInst &RI);
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void visitInstruction(Instruction &I) {
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void visitInstruction(Instruction &I) {
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std::cerr << "Unhandled instruction: " << I;
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std::cerr << "Unhandled instruction: " << I;
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@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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unsigned Class = getClass(C->getType());
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unsigned Class = getClass(C->getType());
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uint64_t Val = CI->getRawValue ();
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switch (Class) {
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switch (Class) {
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case cByte:
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
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return;
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return;
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case cShort: {
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case cShort: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
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.addImm (((uint16_t) Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint16_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cInt: {
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case cInt: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint32_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cLong: {
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case cLong: {
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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uint32_t topHalf, bottomHalf;
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uint32_t topHalf = (uint32_t) (Val >> 32);
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topHalf = (uint32_t) (CI->getRawValue () >> 32);
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uint32_t bottomHalf = (uint32_t)Val;
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bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (bottomHalf & 0x03ff);
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return;
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return;
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}
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}
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default:
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default:
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@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
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return;
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return;
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}
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}
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void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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void V8ISel::visitBinaryOperator (Instruction &I) {
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unsigned DestReg = getReg (I);
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned Op1Reg = getReg (I.getOperand (1));
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@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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case Instruction::And: OpCase = 3; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Shl: OpCase = 6; break;
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case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
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case Instruction::Div:
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case Instruction::Div:
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case Instruction::Rem: {
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case Instruction::Rem: {
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@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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if (OpCase != ~0U) {
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if (OpCase != ~0U) {
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static const unsigned Opcodes[] = {
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static const unsigned Opcodes[] = {
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
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V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
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V8::SLLrr, V8::SRLrr, V8::SRArr
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};
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};
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
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}
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}
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@ -57,9 +57,10 @@ namespace {
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BB = MBBMap[&LLVM_BB];
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BB = MBBMap[&LLVM_BB];
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}
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}
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void visitBinaryOperator(BinaryOperator &I);
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void visitBinaryOperator(Instruction &I);
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void visitCallInst(CallInst &I);
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void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
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void visitReturnInst(ReturnInst &RI);
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void visitCallInst(CallInst &I);
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void visitReturnInst(ReturnInst &RI);
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void visitInstruction(Instruction &I) {
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void visitInstruction(Instruction &I) {
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std::cerr << "Unhandled instruction: " << I;
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std::cerr << "Unhandled instruction: " << I;
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@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
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unsigned Class = getClass(C->getType());
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unsigned Class = getClass(C->getType());
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uint64_t Val = CI->getRawValue ();
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switch (Class) {
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switch (Class) {
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case cByte:
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case cByte:
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
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return;
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return;
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case cShort: {
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case cShort: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
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.addImm (((uint16_t) Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint16_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cInt: {
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case cInt: {
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unsigned TmpReg = makeAnotherReg (C->getType ());
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unsigned TmpReg = makeAnotherReg (C->getType ());
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (((uint32_t) Val) & 0x03ff);
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return;
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return;
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}
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}
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case cLong: {
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case cLong: {
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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unsigned TmpReg = makeAnotherReg (Type::UIntTy);
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uint32_t topHalf, bottomHalf;
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uint32_t topHalf = (uint32_t) (Val >> 32);
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topHalf = (uint32_t) (CI->getRawValue () >> 32);
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uint32_t bottomHalf = (uint32_t)Val;
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bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (topHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
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BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
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.addImm (bottomHalf & 0x03ff);
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return;
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return;
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}
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}
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default:
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default:
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@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
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return;
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return;
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}
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}
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void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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void V8ISel::visitBinaryOperator (Instruction &I) {
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unsigned DestReg = getReg (I);
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unsigned DestReg = getReg (I);
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op0Reg = getReg (I.getOperand (0));
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unsigned Op1Reg = getReg (I.getOperand (1));
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unsigned Op1Reg = getReg (I.getOperand (1));
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@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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case Instruction::And: OpCase = 3; break;
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case Instruction::And: OpCase = 3; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Or: OpCase = 4; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Xor: OpCase = 5; break;
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case Instruction::Shl: OpCase = 6; break;
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case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
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case Instruction::Div:
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case Instruction::Div:
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case Instruction::Rem: {
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case Instruction::Rem: {
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@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
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|||||||
|
|
||||||
if (OpCase != ~0U) {
|
if (OpCase != ~0U) {
|
||||||
static const unsigned Opcodes[] = {
|
static const unsigned Opcodes[] = {
|
||||||
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
|
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
|
||||||
|
V8::SLLrr, V8::SRLrr, V8::SRArr
|
||||||
};
|
};
|
||||||
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
|
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
|
||||||
}
|
}
|
||||||
|
@ -57,9 +57,10 @@ namespace {
|
|||||||
BB = MBBMap[&LLVM_BB];
|
BB = MBBMap[&LLVM_BB];
|
||||||
}
|
}
|
||||||
|
|
||||||
void visitBinaryOperator(BinaryOperator &I);
|
void visitBinaryOperator(Instruction &I);
|
||||||
void visitCallInst(CallInst &I);
|
void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
|
||||||
void visitReturnInst(ReturnInst &RI);
|
void visitCallInst(CallInst &I);
|
||||||
|
void visitReturnInst(ReturnInst &RI);
|
||||||
|
|
||||||
void visitInstruction(Instruction &I) {
|
void visitInstruction(Instruction &I) {
|
||||||
std::cerr << "Unhandled instruction: " << I;
|
std::cerr << "Unhandled instruction: " << I;
|
||||||
@ -169,31 +170,36 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
|
|||||||
Constant *C, unsigned R) {
|
Constant *C, unsigned R) {
|
||||||
if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
|
if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
|
||||||
unsigned Class = getClass(C->getType());
|
unsigned Class = getClass(C->getType());
|
||||||
|
uint64_t Val = CI->getRawValue ();
|
||||||
switch (Class) {
|
switch (Class) {
|
||||||
case cByte:
|
case cByte:
|
||||||
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
|
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
|
||||||
return;
|
return;
|
||||||
case cShort: {
|
case cShort: {
|
||||||
unsigned TmpReg = makeAnotherReg (C->getType ());
|
unsigned TmpReg = makeAnotherReg (C->getType ());
|
||||||
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
|
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
|
||||||
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
|
.addImm (((uint16_t) Val) >> 10);
|
||||||
|
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
|
||||||
|
.addImm (((uint16_t) Val) & 0x03ff);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
case cInt: {
|
case cInt: {
|
||||||
unsigned TmpReg = makeAnotherReg (C->getType ());
|
unsigned TmpReg = makeAnotherReg (C->getType ());
|
||||||
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
|
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
|
||||||
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
|
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
|
||||||
|
.addImm (((uint32_t) Val) & 0x03ff);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
case cLong: {
|
case cLong: {
|
||||||
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
|
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
|
||||||
uint32_t topHalf, bottomHalf;
|
uint32_t topHalf = (uint32_t) (Val >> 32);
|
||||||
topHalf = (uint32_t) (CI->getRawValue () >> 32);
|
uint32_t bottomHalf = (uint32_t)Val;
|
||||||
bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
|
|
||||||
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
|
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
|
||||||
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
|
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
|
||||||
|
.addImm (topHalf & 0x03ff);
|
||||||
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
|
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
|
||||||
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
|
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
|
||||||
|
.addImm (bottomHalf & 0x03ff);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
default:
|
default:
|
||||||
@ -282,7 +288,7 @@ void V8ISel::visitReturnInst(ReturnInst &I) {
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
void V8ISel::visitBinaryOperator (BinaryOperator &I) {
|
void V8ISel::visitBinaryOperator (Instruction &I) {
|
||||||
unsigned DestReg = getReg (I);
|
unsigned DestReg = getReg (I);
|
||||||
unsigned Op0Reg = getReg (I.getOperand (0));
|
unsigned Op0Reg = getReg (I.getOperand (0));
|
||||||
unsigned Op1Reg = getReg (I.getOperand (1));
|
unsigned Op1Reg = getReg (I.getOperand (1));
|
||||||
@ -298,6 +304,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
|
|||||||
case Instruction::And: OpCase = 3; break;
|
case Instruction::And: OpCase = 3; break;
|
||||||
case Instruction::Or: OpCase = 4; break;
|
case Instruction::Or: OpCase = 4; break;
|
||||||
case Instruction::Xor: OpCase = 5; break;
|
case Instruction::Xor: OpCase = 5; break;
|
||||||
|
case Instruction::Shl: OpCase = 6; break;
|
||||||
|
case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
|
||||||
|
|
||||||
case Instruction::Div:
|
case Instruction::Div:
|
||||||
case Instruction::Rem: {
|
case Instruction::Rem: {
|
||||||
@ -332,7 +340,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
|
|||||||
|
|
||||||
if (OpCase != ~0U) {
|
if (OpCase != ~0U) {
|
||||||
static const unsigned Opcodes[] = {
|
static const unsigned Opcodes[] = {
|
||||||
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr
|
V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
|
||||||
|
V8::SLLrr, V8::SRLrr, V8::SRArr
|
||||||
};
|
};
|
||||||
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
|
BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
|
||||||
}
|
}
|
||||||
|
Loading…
x
Reference in New Issue
Block a user