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More C++ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Smith
@@ -42,11 +42,9 @@ namespace X86Disassembler {
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#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
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#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
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/*
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* Attributes of an instruction that must be known before the opcode can be
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* processed correctly. Most of these indicate the presence of particular
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* prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
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*/
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// Attributes of an instruction that must be known before the opcode can be
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// processed correctly. Most of these indicate the presence of particular
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// prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
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#define ATTRIBUTE_BITS \
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ENUM_ENTRY(ATTR_NONE, 0x00) \
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ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
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@@ -71,13 +69,11 @@ enum attributeBits {
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};
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#undef ENUM_ENTRY
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/*
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* Combinations of the above attributes that are relevant to instruction
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* decode. Although other combinations are possible, they can be reduced to
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* these without affecting the ultimately decoded instruction.
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*/
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// Combinations of the above attributes that are relevant to instruction
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// decode. Although other combinations are possible, they can be reduced to
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// these without affecting the ultimately decoded instruction.
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/* Class name Rank Rationale for rank assignment */
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// Class name Rank Rationale for rank assignment
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#define INSTRUCTION_CONTEXTS \
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ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
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ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
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@@ -278,10 +274,8 @@ enum InstructionContext {
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};
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#undef ENUM_ENTRY
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/*
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* Opcode types, which determine which decode table to use, both in the Intel
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* manual and also for the decoder.
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*/
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// Opcode types, which determine which decode table to use, both in the Intel
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// manual and also for the decoder.
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enum OpcodeType {
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ONEBYTE = 0,
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TWOBYTE = 1,
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@@ -292,37 +286,31 @@ enum OpcodeType {
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XOPA_MAP = 6
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};
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/*
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* The following structs are used for the hierarchical decode table. After
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* determining the instruction's class (i.e., which IC_* constant applies to
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* it), the decoder reads the opcode. Some instructions require specific
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* values of the ModR/M byte, so the ModR/M byte indexes into the final table.
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*
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* If a ModR/M byte is not required, "required" is left unset, and the values
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* for each instructionID are identical.
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*/
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// The following structs are used for the hierarchical decode table. After
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// determining the instruction's class (i.e., which IC_* constant applies to
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// it), the decoder reads the opcode. Some instructions require specific
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// values of the ModR/M byte, so the ModR/M byte indexes into the final table.
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//
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// If a ModR/M byte is not required, "required" is left unset, and the values
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// for each instructionID are identical.
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typedef uint16_t InstrUID;
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/*
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* ModRMDecisionType - describes the type of ModR/M decision, allowing the
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* consumer to determine the number of entries in it.
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*
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* MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
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* instruction is the same.
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* MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
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* corresponds to one instruction; otherwise, it corresponds to
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* a different instruction.
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* MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
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* divided by 8 is used to select instruction; otherwise, each
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* value of the ModR/M byte could correspond to a different
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* instruction.
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* MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
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corresponds to instructions that use reg field as opcode
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* MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
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* to a different instruction.
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*/
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// ModRMDecisionType - describes the type of ModR/M decision, allowing the
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// consumer to determine the number of entries in it.
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//
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// MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
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// instruction is the same.
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// MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
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// corresponds to one instruction; otherwise, it corresponds to
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// a different instruction.
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// MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
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// divided by 8 is used to select instruction; otherwise, each
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// value of the ModR/M byte could correspond to a different
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// instruction.
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// MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
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// corresponds to instructions that use reg field as opcode
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// MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
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// to a different instruction.
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#define MODRMTYPES \
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ENUM_ENTRY(MODRM_ONEENTRY) \
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ENUM_ENTRY(MODRM_SPLITRM) \
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@@ -337,10 +325,7 @@ enum ModRMDecisionType {
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};
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#undef ENUM_ENTRY
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/*
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* Physical encodings of instruction operands.
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*/
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// Physical encodings of instruction operands.
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#define ENCODINGS \
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ENUM_ENTRY(ENCODING_NONE, "") \
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ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
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@@ -381,10 +366,7 @@ enum OperandEncoding {
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};
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#undef ENUM_ENTRY
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/*
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* Semantic interpretations of instruction operands.
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*/
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// Semantic interpretations of instruction operands.
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#define TYPES \
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ENUM_ENTRY(TYPE_NONE, "") \
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ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \
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@@ -481,20 +463,14 @@ enum OperandType {
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};
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#undef ENUM_ENTRY
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/*
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* OperandSpecifier - The specification for how to extract and interpret one
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* operand.
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*/
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/// \brief The specification for how to extract and interpret one operand.
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struct OperandSpecifier {
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uint8_t encoding;
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uint8_t type;
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};
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/*
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* Indicates where the opcode modifier (if any) is to be found. Extended
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* opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
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*/
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// Indicates where the opcode modifier (if any) is to be found. Extended
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// opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
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#define MODIFIER_TYPES \
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ENUM_ENTRY(MODIFIER_NONE)
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@@ -505,13 +481,11 @@ enum ModifierType {
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};
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#undef ENUM_ENTRY
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#define X86_MAX_OPERANDS 5
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static const int X86_MAX_OPERANDS = 5;
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/*
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* Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
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* are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
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* respectively.
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*/
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/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
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/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
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/// respectively.
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enum DisassemblerMode {
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MODE_16BIT,
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MODE_32BIT,
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