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Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,6 +33,10 @@ class TargetSubtarget {
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protected: // Can only create subclasses...
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TargetSubtarget();
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public:
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// AntiDepBreakMode - Type of anti-dependence breaking that should
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// be performed before post-RA scheduling.
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typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
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virtual ~TargetSubtarget();
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/// getSpecialAddressLatency - For targets where it is beneficial to
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@ -43,8 +47,10 @@ public:
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// enablePostRAScheduler - If the target can benefit from post-regalloc
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// scheduling and the specified optimization level meets the requirement
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// return true to enable post-register-allocation scheduling.
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virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
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// return true to enable post-register-allocation scheduling.
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virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& mode) const {
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mode = ANTIDEP_NONE;
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return false;
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}
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@ -128,6 +128,9 @@ namespace {
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/// AA - AliasAnalysis for making memory reference queries.
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AliasAnalysis *AA;
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/// AntiDepMode - Anti-dependence breaking mode
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TargetSubtarget::AntiDepBreakMode AntiDepMode;
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/// Classes - For live regs that are only used in one register class in a
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/// live range, the register class. If the register is not live, the
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/// corresponding value is null. If the register is live but used in
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@ -156,10 +159,11 @@ namespace {
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const MachineLoopInfo &MLI,
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const MachineDominatorTree &MDT,
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ScheduleHazardRecognizer *HR,
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AliasAnalysis *aa)
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AliasAnalysis *aa,
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TargetSubtarget::AntiDepBreakMode adm)
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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HazardRec(HR), AA(aa) {}
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HazardRec(HR), AA(aa), AntiDepMode(adm) {}
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~SchedulePostRATDList() {
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delete HazardRec;
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@ -234,16 +238,23 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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AA = &getAnalysis<AliasAnalysis>();
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// Check for explicit enable/disable of post-ra scheduling.
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TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
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if (EnablePostRAScheduler.getPosition() > 0) {
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if (!EnablePostRAScheduler)
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return false;
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} else {
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// Check that post-RA scheduling is enabled for this target.
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const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
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if (!ST.enablePostRAScheduler(OptLevel))
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if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode))
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return false;
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}
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// Check for antidep breaking override...
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if (EnableAntiDepBreaking.getPosition() > 0) {
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AntiDepMode = (EnableAntiDepBreaking) ?
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TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
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}
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DEBUG(errs() << "PostRAScheduler\n");
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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@ -253,7 +264,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
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(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA);
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, AA, AntiDepMode);
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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@ -393,7 +404,7 @@ void SchedulePostRATDList::Schedule() {
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// Build the scheduling graph.
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BuildSchedGraph(AA);
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if (EnableAntiDepBreaking) {
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if (AntiDepMode != TargetSubtarget::ANTIDEP_NONE) {
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if (BreakAntiDependencies()) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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@ -128,7 +128,9 @@ protected:
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/// enablePostRAScheduler - True at 'More' optimization except
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/// for Thumb1.
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& mode) const {
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mode = TargetSubtarget::ANTIDEP_NONE;
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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@ -218,7 +218,9 @@ public:
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/// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
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/// at 'More' optimization level.
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
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bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& mode) const {
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mode = TargetSubtarget::ANTIDEP_NONE;
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return OptLevel >= CodeGenOpt::Default;
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}
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};
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@ -11,11 +11,11 @@ define float @foo(float %x) nounwind {
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%tmp14 = fadd float %tmp12, %tmp7
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ret float %tmp14
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; CHECK: mulss LCPI1_3(%rip)
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; CHECK-NEXT: mulss LCPI1_0(%rip)
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; CHECK: mulss LCPI1_0(%rip)
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; CHECK-NEXT: mulss LCPI1_1(%rip)
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; CHECK-NEXT: mulss LCPI1_2(%rip)
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; CHECK-NEXT: addss
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; CHECK: mulss LCPI1_3(%rip)
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; CHECK-NEXT: mulss LCPI1_2(%rip)
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; CHECK-NEXT: addss
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; CHECK-NEXT: addss
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; CHECK-NEXT: ret
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@ -10,10 +10,10 @@ define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
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; CHECK: t1:
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; CHECK: movl 8(%esp), %eax
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; CHECK-NEXT: movl 4(%esp), %ecx
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; CHECK-NEXT: movapd (%eax), %xmm0
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; CHECK-NEXT: movl 4(%esp), %eax
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; CHECK-NEXT: movlpd 12(%esp), %xmm0
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; CHECK-NEXT: movapd %xmm0, (%ecx)
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; CHECK-NEXT: movapd %xmm0, (%eax)
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; CHECK-NEXT: ret
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}
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@ -26,9 +26,9 @@ define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
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; CHECK: t2:
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; CHECK: movl 8(%esp), %eax
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; CHECK-NEXT: movl 4(%esp), %ecx
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; CHECK-NEXT: movapd (%eax), %xmm0
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; CHECK-NEXT: movl 4(%esp), %eax
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; CHECK-NEXT: movhpd 12(%esp), %xmm0
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; CHECK-NEXT: movapd %xmm0, (%ecx)
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; CHECK-NEXT: movapd %xmm0, (%eax)
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; CHECK-NEXT: ret
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}
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@ -168,11 +168,11 @@ define internal void @t10() nounwind {
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ret void
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; X64: t10:
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; X64: pextrw $4, %xmm0, %eax
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; X64: pextrw $6, %xmm0, %edx
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; X64: movlhps %xmm1, %xmm1
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; X64: pshuflw $8, %xmm1, %xmm1
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; X64: pinsrw $2, %eax, %xmm1
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; X64: pinsrw $3, %edx, %xmm1
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; X64: pextrw $6, %xmm0, %eax
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; X64: pinsrw $3, %eax, %xmm1
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}
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@ -63,7 +63,7 @@ entry:
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; CHECK: shift3b:
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; CHECK: movzwl
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; CHECK: movd
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; CHECK-NEXT: psllw
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; CHECK: psllw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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@ -63,7 +63,7 @@ entry:
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; CHECK: shift3b:
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; CHECK: movzwl
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; CHECK: movd
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; CHECK-NEXT: psrlw
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; CHECK: psrlw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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@ -52,7 +52,7 @@ entry:
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; CHECK: shift3b:
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; CHECK: movzwl
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; CHECK: movd
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; CHECK-NEXT: psraw
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; CHECK: psraw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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@ -6,7 +6,7 @@ define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5a:
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; CHECK: movd
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; CHECK-NEXT: pslld
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; CHECK: pslld
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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@ -20,7 +20,7 @@ define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5b:
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; CHECK: movd
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; CHECK-NEXT: psrad
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; CHECK: psrad
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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