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https://github.com/c64scene-ar/llvm-6502.git
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implement mips16 patterns for select nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
32ff623c8b
commit
4c5a6dab17
@ -228,6 +228,95 @@ class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// These Sel patterns support the generation of conditional move
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// pseudo instructions.
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//
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// The nomenclature uses the components making up the pseudo and may
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// be a bit counter intuitive when compared with the end result we seek.
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// For example using a bqez in the example directly below results in the
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// conditional move being done if the tested register is not zero.
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// I considered in easier to check by keeping the pseudo consistent with
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// it's components but it could have been done differently.
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//
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// The simplest case is when can test and operand directly and do the
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// conditional move based on a simple mips16 conditional
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// branch instruction.
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// for example:
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// if $op == beqz or bnez:
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//
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// $op1 $rt, .+4
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// move $rd, $rs
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//
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// if $op == beqz, then if $rt != 0, then the conditional assignment
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// $rd = $rs is done.
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// if $op == bnez, then if $rt == 0, then the conditional assignment
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// $rd = $rs is done.
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//
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// So this pseudo class only has one operand, i.e. op
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//
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class Sel<bits<5> f1, string op, InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rt),
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!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin,
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Pseudo16> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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//
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// The next two instruction classes allow for an operand which tests
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// two operands and returns a value in register T8 and
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//then does a conditional branch based on the value of T8
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//
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// op2 can be cmpi or slti/sltiu
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// op1 can bteqz or btnez
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// the operands for op2 are a register and a signed constant
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//
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// $op2 $t, $imm ;test register t and branch conditionally
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// $op1 .+4 ;op1 is a conditional branch
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// move $rd, $rs
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//
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//
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class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
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InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, simm16:$imm),
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!strconcat(op2,
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!strconcat("\t$rl, $imm\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
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Pseudo16> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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//
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// op2 can be cmp or slt/sltu
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// op1 can be bteqz or btnez
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// the operands for op2 are two registers
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// op1 is a conditional branch
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//
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//
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// $op2 $rl, $rr ;test registers rl,rr
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// $op1 .+4 ;op2 is a conditional branch
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// move $rd, $rs
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//
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//
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class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
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InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, CPU16Regs:$rr),
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!strconcat(op2,
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!strconcat("\t$rl, $rr\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
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Pseudo16> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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//
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// Some general instruction class info
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//
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@ -564,6 +653,120 @@ def SaveRaF16:
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def SbRxRyOffMemX16:
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FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
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//
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// The Sel(T) instructions are pseudos
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// T means that they use T8 implicitly.
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//
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//
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// Format: SelBeqZ rd, rs, rt
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// Purpose: if rt==0, do nothing
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// else rs = rt
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//
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def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
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//
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// Format: SelTBteqZCmp rd, rs, rl, rr
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// Purpose: b = Cmp rl, rr.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
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//
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// Format: SelTBteqZCmpi rd, rs, rl, rr
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// Purpose: b = Cmpi rl, imm.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
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//
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// Format: SelTBteqZSlt rd, rs, rl, rr
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// Purpose: b = Slt rl, rr.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
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//
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// Format: SelTBteqZSlti rd, rs, rl, rr
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// Purpose: b = Slti rl, imm.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
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//
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// Format: SelTBteqZSltu rd, rs, rl, rr
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// Purpose: b = Sltu rl, rr.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
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//
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// Format: SelTBteqZSltiu rd, rs, rl, rr
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// Purpose: b = Sltiu rl, imm.
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
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//
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// Format: SelBnez rd, rs, rt
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// Purpose: if rt!=0, do nothing
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// else rs = rt
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//
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def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
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//
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// Format: SelTBtneZCmp rd, rs, rl, rr
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// Purpose: b = Cmp rl, rr.
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// If b!=0 then do nothing.
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// if b0=0 then rd = rs
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//
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def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
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//
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// Format: SelTBtnezCmpi rd, rs, rl, rr
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// Purpose: b = Cmpi rl, imm.
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
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//
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// Format: SelTBtneZSlt rd, rs, rl, rr
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// Purpose: b = Slt rl, rr.
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
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//
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// Format: SelTBtneZSlti rd, rs, rl, rr
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// Purpose: b = Slti rl, imm.
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
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//
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// Format: SelTBtneZSltu rd, rs, rl, rr
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// Purpose: b = Sltu rl, rr.
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
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//
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// Format: SelTBtneZSltiu rd, rs, rl, rr
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// Purpose: b = Slti rl, imm.
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
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//
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//
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// Format: SH ry, offset(rx) MIPS16e
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// Purpose: Store Halfword (Extended)
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@ -766,7 +969,7 @@ class SetCC_R16<PatFrag cond_op, Instruction I>:
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class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
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Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
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(I CPU16Regs:$rx, imm_type:$imm16)>;
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(I CPU16Regs:$rx, imm_type:$imm16)>;
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//
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@ -922,6 +1125,180 @@ def: Mips16Pat
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<(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
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(DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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// signed a,b
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// x = (a>=b)?x:y
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//
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// if !(a < b) x = y
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//
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def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a, CPU16Regs:$b)>;
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// signed a,b
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// x = (a>b)?x:y
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//
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// if (b < a) x = y
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//
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def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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// unsigned a,b
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// x = (a>=b)?x:y
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//
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// if !(a < b) x = y;
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//
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def : Mips16Pat<
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(select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a, CPU16Regs:$b)>;
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// unsigned a,b
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// x = (a>b)?x:y
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//
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// if (b < a) x = y
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//
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def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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// signed
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// x = (a >= k)?x:y
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// due to an llvm optimization, i don't think that this will ever
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// be used. This is transformed into x = (a > k-1)?x:y
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//
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//
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//def : Mips16Pat<
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// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
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// CPU16Regs:$T, CPU16Regs:$F),
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// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
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// CPU16Regs:$lhs, immSExt16:$rhs)>;
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//def : Mips16Pat<
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// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
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// CPU16Regs:$T, CPU16Regs:$F),
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// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
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// CPU16Regs:$lhs, immSExt16:$rhs)>;
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// signed
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// x = (a < k)?x:y
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//
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// if !(a < k) x = y;
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//
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def : Mips16Pat<
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(select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a, immSExt16:$b)>;
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//
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//
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// signed
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// x = (a <= b)? x : y
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//
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// if (b < a) x = y
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//
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def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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//
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// unnsigned
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// x = (a <= b)? x : y
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//
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// if (b < a) x = y
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//
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def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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//
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// signed/unsigned
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// x = (a == b)? x : y
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//
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// if (a != b) x = y
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//
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def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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//
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// signed/unsigned
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// x = (a == 0)? x : y
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//
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// if (a != 0) x = y
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//
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def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a)>;
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//
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// signed/unsigned
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// x = (a == k)? x : y
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//
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// if (a != k) x = y
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//
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def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a, immZExt16:$k)>;
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//
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// signed/unsigned
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// x = (a != b)? x : y
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//
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// if (a == b) x = y
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//
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//
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def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$b, CPU16Regs:$a)>;
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//
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// signed/unsigned
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// x = (a != 0)? x : y
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//
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// if (a == 0) x = y
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//
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def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelBneZ CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a)>;
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// signed/unsigned
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// x = (a)? x : y
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//
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// if (!a) x = y
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//
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def : Mips16Pat<(select CPU16Regs:$a,
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CPU16Regs:$x, CPU16Regs:$y),
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(SelBneZ CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a)>;
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//
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// signed/unsigned
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// x = (a != k)? x : y
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//
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// if (a == k) x = y
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//
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def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
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CPU16Regs:$x, CPU16Regs:$y),
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(SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
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CPU16Regs:$a, immZExt16:$k)>;
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//
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// When writing C code to test setxx these patterns,
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@ -1013,7 +1390,7 @@ def: Mips16Pat
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//def: Mips16Pat
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// <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
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// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
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// (LiRxImmX16 1))>;
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// (LiRxImmX16 1))>;
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//
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// setugt
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350
test/CodeGen/Mips/selpat.ll
Normal file
350
test/CodeGen/Mips/selpat.ll
Normal file
@ -0,0 +1,350 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@t = global i32 10, align 4
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@f = global i32 199, align 4
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@a = global i32 1, align 4
|
||||
@b = global i32 10, align 4
|
||||
@c = global i32 1, align 4
|
||||
@z1 = common global i32 0, align 4
|
||||
@z2 = common global i32 0, align 4
|
||||
@z3 = common global i32 0, align 4
|
||||
@z4 = common global i32 0, align 4
|
||||
|
||||
define void @calc_seleq() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp eq i32 %0, %1
|
||||
%2 = load i32* @f, align 4
|
||||
%3 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
store i32 %cond, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp eq i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %3, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
store i32 %cond10, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @calc_seleqk() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%cmp = icmp eq i32 %0, 1
|
||||
%1 = load i32* @t, align 4
|
||||
%2 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: cmpi ${{[0-9]+}}, 1
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp eq i32 %0, 10
|
||||
%cond5 = select i1 %cmp1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%3 = load i32* @b, align 4
|
||||
%cmp6 = icmp eq i32 %3, 3
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %1
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
; 16: cmpi ${{[0-9]+}}, 10
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp11 = icmp eq i32 %3, 10
|
||||
%cond15 = select i1 %cmp11, i32 %1, i32 %2
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_seleqz() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%cmp = icmp eq i32 %0, 0
|
||||
%1 = load i32* @t, align 4
|
||||
%2 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: beqz ${{[0-9]+}}, .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%3 = load i32* @b, align 4
|
||||
%cmp1 = icmp eq i32 %3, 0
|
||||
%cond5 = select i1 %cmp1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp eq i32 %4, 0
|
||||
%cond10 = select i1 %cmp6, i32 %1, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
store i32 %cond, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selge() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp sge i32 %0, %1
|
||||
%2 = load i32* @f, align 4
|
||||
%3 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp sge i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp sge i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %3, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp sge i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %3, i32 %2
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define i32 @calc_selgt() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp sgt i32 %0, %1
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%2 = load i32* @f, align 4
|
||||
%3 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
%cmp1 = icmp sgt i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp sgt i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %3
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp sgt i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %2, i32 %3
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret i32 undef
|
||||
}
|
||||
|
||||
define void @calc_selle() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp sle i32 %0, %1
|
||||
%2 = load i32* @t, align 4
|
||||
%3 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp sle i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp sle i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %3
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp sle i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %2, i32 %3
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selltk() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%cmp = icmp slt i32 %0, 10
|
||||
%1 = load i32* @t, align 4
|
||||
%2 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: slti ${{[0-9]+}}, {{[0-9]+}}
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%3 = load i32* @b, align 4
|
||||
%cmp1 = icmp slt i32 %3, 2
|
||||
%cond5 = select i1 %cmp1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp sgt i32 %4, 2
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %1
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp sgt i32 %0, 2
|
||||
%cond15 = select i1 %cmp11, i32 %2, i32 %1
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
define void @calc_selne() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp ne i32 %0, %1
|
||||
%2 = load i32* @t, align 4
|
||||
%3 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
store i32 %cond, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp ne i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %3, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
store i32 %cond10, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selnek() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%cmp = icmp ne i32 %0, 1
|
||||
%1 = load i32* @f, align 4
|
||||
%2 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: cmpi ${{[0-9]+}}, 1
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp ne i32 %0, 10
|
||||
%cond5 = select i1 %cmp1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%3 = load i32* @b, align 4
|
||||
%cmp6 = icmp ne i32 %3, 3
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %1
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
; 16: cmpi ${{[0-9]+}}, 10
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp11 = icmp ne i32 %3, 10
|
||||
%cond15 = select i1 %cmp11, i32 %1, i32 %2
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selnez() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%cmp = icmp ne i32 %0, 0
|
||||
%1 = load i32* @f, align 4
|
||||
%2 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: bnez ${{[0-9]+}}, .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%3 = load i32* @b, align 4
|
||||
%cmp1 = icmp ne i32 %3, 0
|
||||
%cond5 = select i1 %cmp1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp ne i32 %4, 0
|
||||
%cond10 = select i1 %cmp6, i32 %1, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
store i32 %cond, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selnez2() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%tobool = icmp ne i32 %0, 0
|
||||
%1 = load i32* @f, align 4
|
||||
%2 = load i32* @t, align 4
|
||||
%cond = select i1 %tobool, i32 %1, i32 %2
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: bnez ${{[0-9]+}}, .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%3 = load i32* @b, align 4
|
||||
%tobool1 = icmp ne i32 %3, 0
|
||||
%cond5 = select i1 %tobool1, i32 %2, i32 %1
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%tobool6 = icmp ne i32 %4, 0
|
||||
%cond10 = select i1 %tobool6, i32 %1, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
store i32 %cond, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_seluge() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp uge i32 %0, %1
|
||||
%2 = load i32* @f, align 4
|
||||
%3 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp uge i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp uge i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %3, i32 %2
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp uge i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %3, i32 %2
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selugt() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp ugt i32 %0, %1
|
||||
%2 = load i32* @f, align 4
|
||||
%3 = load i32* @t, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp ugt i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp ugt i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %3
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp ugt i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %2, i32 %3
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @calc_selule() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @a, align 4
|
||||
%1 = load i32* @b, align 4
|
||||
%cmp = icmp ule i32 %0, %1
|
||||
%2 = load i32* @t, align 4
|
||||
%3 = load i32* @f, align 4
|
||||
%cond = select i1 %cmp, i32 %2, i32 %3
|
||||
store i32 %cond, i32* @z1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz .+4
|
||||
; 16: move ${{[0-9]+}}, ${{[0-9]+}}
|
||||
%cmp1 = icmp ule i32 %1, %0
|
||||
%cond5 = select i1 %cmp1, i32 %3, i32 %2
|
||||
store i32 %cond5, i32* @z2, align 4
|
||||
%4 = load i32* @c, align 4
|
||||
%cmp6 = icmp ule i32 %4, %0
|
||||
%cond10 = select i1 %cmp6, i32 %2, i32 %3
|
||||
store i32 %cond10, i32* @z3, align 4
|
||||
%cmp11 = icmp ule i32 %0, %4
|
||||
%cond15 = select i1 %cmp11, i32 %2, i32 %3
|
||||
store i32 %cond15, i32* @z4, align 4
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user