From 4c5aebe89dd5548439503ab4efa525e0db81e342 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 9 Mar 2015 18:49:45 +0000 Subject: [PATCH] R600/SI: Refactor DS instruction defs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231683 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstrFormats.td | 6 + lib/Target/R600/SIInstrInfo.td | 246 +++++++++++------------------- lib/Target/R600/SIInstructions.td | 48 +++--- 3 files changed, 121 insertions(+), 179 deletions(-) diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index c90c741b028..544e61dde79 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -577,6 +577,12 @@ class DS pattern> : let DS = 1; let UseNamedOperandTable = 1; let DisableEncoding = "$m0"; + + // Most instruction load and store data, so set this as the default. + let mayLoad = 1; + let mayStore = 1; + + let hasSideEffects = 0; let SchedRW = [WriteLDS]; } diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 3f073fd54f1..2830f0672b6 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -1483,10 +1483,8 @@ class DS_Real_vi op, string opName, dag outs, dag ins, string asm> : DSe_vi , SIMCInstr ; -class DS_1A_Real_si op, string opName, dag outs, dag ins, string asm> : - DS , - DSe , - SIMCInstr { +class DS_Off16_Real_si op, string opName, dag outs, dag ins, string asm> : + DS_Real_si { // Single load interpret the 2 i8imm operands as a single i16 offset. bits<16> offset; @@ -1494,10 +1492,8 @@ class DS_1A_Real_si op, string opName, dag outs, dag ins, string asm> : let offset1 = offset{15-8}; } -class DS_1A_Real_vi op, string opName, dag outs, dag ins, string asm> : - DS , - DSe_vi , - SIMCInstr { +class DS_Off16_Real_vi op, string opName, dag outs, dag ins, string asm> : + DS_Real_vi { // Single load interpret the 2 i8imm operands as a single i16 offset. bits<16> offset; @@ -1505,181 +1501,113 @@ class DS_1A_Real_vi op, string opName, dag outs, dag ins, string asm> : let offset1 = offset{15-8}; } -multiclass DS_1A_Load_m op, string opName, dag outs, dag ins, string asm, - list pat> { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { - def "" : DS_Pseudo ; +multiclass DS_1A_RET op, string opName, RegisterClass rc, + dag outs = (outs rc:$vdst), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0), + string asm = opName#" $vdst, $addr"#"$offset"> { - let data0 = 0, data1 = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } + def "" : DS_Pseudo ; + + let data0 = 0, data1 = 0 in { + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } } -multiclass DS_Load_Helper op, string asm, RegisterClass regClass> - : DS_1A_Load_m < - op, - asm, - (outs regClass:$vdst), - (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0), - asm#" $vdst, $addr"#"$offset", - []>; +multiclass DS_1A_Off8_RET op, string opName, RegisterClass rc, + dag outs = (outs rc:$vdst), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, + ds_offset1:$offset1, M0Reg:$m0), + string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1"> { -multiclass DS_Load2_m op, string opName, dag outs, dag ins, string asm, - list pat> { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { - def "" : DS_Pseudo ; + def "" : DS_Pseudo ; - let data0 = 0, data1 = 0 in { - def _si : DS_Real_si ; - def _vi : DS_Real_vi ; - } + let data0 = 0, data1 = 0 in { + def _si : DS_Real_si ; + def _vi : DS_Real_vi ; } } -multiclass DS_Load2_Helper op, string asm, RegisterClass regClass> - : DS_Load2_m < - op, - asm, - (outs regClass:$vdst), - (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1, - M0Reg:$m0), - asm#" $vdst, $addr"#"$offset0"#"$offset1", - []>; +multiclass DS_1A1D_NORET op, string opName, RegisterClass rc, + dag outs = (outs), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, + M0Reg:$m0), + string asm = opName#" $addr, $data0"#"$offset"> { -multiclass DS_1A_Store_m op, string opName, dag outs, dag ins, - string asm, list pat> { - let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { - def "" : DS_Pseudo ; + def "" : DS_Pseudo , + AtomicNoRet; - let data1 = 0, vdst = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } + let data1 = 0, vdst = 0 in { + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } } -multiclass DS_Store_Helper op, string asm, RegisterClass regClass> - : DS_1A_Store_m < - op, - asm, - (outs), - (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0), - asm#" $addr, $data0"#"$offset", - []>; +multiclass DS_1A1D_Off8_NORET op, string opName, RegisterClass rc, + dag outs = (outs), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, + ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0), + string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"> { -multiclass DS_Store_m op, string opName, dag outs, dag ins, - string asm, list pat> { - let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { - def "" : DS_Pseudo ; + def "" : DS_Pseudo ; - let vdst = 0 in { - def _si : DS_Real_si ; - def _vi : DS_Real_vi ; - } + let vdst = 0 in { + def _si : DS_Real_si ; + def _vi : DS_Real_vi ; } } -multiclass DS_Store2_Helper op, string asm, RegisterClass regClass> - : DS_Store_m < - op, - asm, - (outs), - (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1, - ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0), - asm#" $addr, $data0, $data1"#"$offset0"#"$offset1", - []>; +multiclass DS_1A1D_RET op, string opName, RegisterClass rc, + string noRetOp = "", + dag outs = (outs rc:$vdst), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, + M0Reg:$m0), + string asm = opName#" $vdst, $addr, $data0"#"$offset"> { -// 1 address, 1 data. -multiclass DS_1A1D_RET_m op, string opName, dag outs, dag ins, - string asm, list pat, string noRetOp> { - let mayLoad = 1, mayStore = 1, - hasPostISelHook = 1 // Adjusted to no return version. - in { - def "" : DS_Pseudo , - AtomicNoRet; + def "" : DS_Pseudo , + AtomicNoRet; - let data1 = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } + let data1 = 0 in { + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } } -multiclass DS_1A1D_RET op, string asm, RegisterClass rc, - string noRetOp = ""> : DS_1A1D_RET_m < - op, asm, - (outs rc:$vdst), - (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0), - asm#" $vdst, $addr, $data0"#"$offset", [], noRetOp>; +multiclass DS_1A2D_RET_m op, string opName, RegisterClass rc, + string noRetOp = "", dag ins, + dag outs = (outs rc:$vdst), + string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"> { -// 1 address, 2 data. -multiclass DS_1A2D_RET_m op, string opName, dag outs, dag ins, - string asm, list pat, string noRetOp> { - let mayLoad = 1, mayStore = 1, - hasPostISelHook = 1 // Adjusted to no return version. - in { - def "" : DS_Pseudo , - AtomicNoRet; + def "" : DS_Pseudo , + AtomicNoRet; - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } multiclass DS_1A2D_RET op, string asm, RegisterClass rc, - string noRetOp = "", RegisterClass src = rc> : DS_1A2D_RET_m < - op, asm, - (outs rc:$vdst), - (ins i1imm:$gds, VGPR_32:$addr, src:$data0, src:$data1, ds_offset:$offset, M0Reg:$m0), - asm#" $vdst, $addr, $data0, $data1"#"$offset", - [], noRetOp>; + string noRetOp = "", RegisterClass src = rc> : + DS_1A2D_RET_m ; -// 1 address, 2 data. -multiclass DS_1A2D_NORET_m op, string opName, dag outs, dag ins, - string asm, list pat, string noRetOp> { - let mayLoad = 1, mayStore = 1 in { - def "" : DS_Pseudo , - AtomicNoRet; +multiclass DS_1A2D_NORET op, string opName, RegisterClass rc, + string noRetOp = opName, + dag outs = (outs), + dag ins = (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, + ds_offset:$offset, M0Reg:$m0), + string asm = opName#" $addr, $data0, $data1"#"$offset"> { - let vdst = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } + def "" : DS_Pseudo , + AtomicNoRet; + + let vdst = 0 in { + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } } -multiclass DS_1A2D_NORET op, string asm, RegisterClass rc, - string noRetOp = asm> : DS_1A2D_NORET_m < - op, asm, - (outs), - (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0), - asm#" $addr, $data0, $data1"#"$offset", - [], noRetOp>; - -// 1 address, 1 data. -multiclass DS_1A1D_NORET_m op, string opName, dag outs, dag ins, - string asm, list pat, string noRetOp> { - let mayLoad = 1, mayStore = 1 in { - def "" : DS_Pseudo , - AtomicNoRet; - - let data1 = 0, vdst = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } - } -} - -multiclass DS_1A1D_NORET op, string asm, RegisterClass rc, - string noRetOp = asm> : DS_1A1D_NORET_m < - op, asm, - (outs), - (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0), - asm#" $addr, $data0"#"$offset", - [], noRetOp>; - multiclass DS_0A_RET op, string opName, dag outs = (outs VGPR_32:$vdst), dag ins = (ins i1imm:$gds, ds_offset:$offset, M0Reg:$m0), @@ -1689,8 +1617,8 @@ multiclass DS_0A_RET op, string opName, def "" : DS_Pseudo ; let addr = 0, data0 = 0, data1 = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } // end addr = 0, data0 = 0, data1 = 0 } // end mayLoad = 1, mayStore = 1 } @@ -1700,14 +1628,12 @@ multiclass DS_1A_RET_GDS op, string opName, dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0), string asm = opName#" $vdst, $addr $offset"> { - let mayLoad = 1, mayStore = 1 in { - def "" : DS_Pseudo ; + def "" : DS_Pseudo ; - let data0 = 0, data1 = 0, gds = 1 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; - } // end data0 = 0, data1 = 0, gds = 1 - } // end mayLoad = 1, mayStore = 1 + let data0 = 0, data1 = 0, gds = 1 in { + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; + } // end data0 = 0, data1 = 0, gds = 1 } multiclass DS_1A_GDS op, string opName, @@ -1732,8 +1658,8 @@ multiclass DS_1A op, string opName, def "" : DS_Pseudo ; let vdst = 0, data0 = 0, data1 = 0 in { - def _si : DS_1A_Real_si ; - def _vi : DS_1A_Real_vi ; + def _si : DS_Off16_Real_si ; + def _vi : DS_Off16_Real_vi ; } // let vdst = 0, data0 = 0, data1 = 0 } // end mayLoad = 1, mayStore = 1 } diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index a29e0cdca15..b0025dc03bc 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -784,9 +784,11 @@ defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; -defm DS_WRITE_B32 : DS_Store_Helper <0xd, "ds_write_b32", VGPR_32>; -defm DS_WRITE2_B32 : DS_Store2_Helper <0xe, "ds_write2_b32", VGPR_32>; -defm DS_WRITE2ST64_B32 : DS_Store2_Helper <0xf, "ds_write2st64_b32", VGPR_32>; +let mayLoad = 0 in { +defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; +defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; +defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; +} defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; @@ -797,8 +799,10 @@ defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; -defm DS_WRITE_B8 : DS_Store_Helper <0x1e, "ds_write_b8", VGPR_32>; -defm DS_WRITE_B16 : DS_Store_Helper <0x1f, "ds_write_b16", VGPR_32>; +let mayLoad = 0 in { +defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; +defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; +} defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; @@ -826,14 +830,16 @@ defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32" let SubtargetPredicate = isCI in { defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">; } // End isCI -defm DS_SWIZZLE_B32 : DS_Load_Helper <0x35, "ds_swizzle_b32", VGPR_32>; -defm DS_READ_B32 : DS_Load_Helper <0x36, "ds_read_b32", VGPR_32>; -defm DS_READ2_B32 : DS_Load2_Helper <0x37, "ds_read2_b32", VReg_64>; -defm DS_READ2ST64_B32 : DS_Load2_Helper <0x38, "ds_read2st64_b32", VReg_64>; -defm DS_READ_I8 : DS_Load_Helper <0x39, "ds_read_i8", VGPR_32>; -defm DS_READ_U8 : DS_Load_Helper <0x3a, "ds_read_u8", VGPR_32>; -defm DS_READ_I16 : DS_Load_Helper <0x3b, "ds_read_i16", VGPR_32>; -defm DS_READ_U16 : DS_Load_Helper <0x3c, "ds_read_u16", VGPR_32>; +defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; +let mayStore = 0 in { +defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; +defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; +defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; +defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; +defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; +defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; +defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; +} defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; @@ -850,9 +856,11 @@ defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; -defm DS_WRITE_B64 : DS_Store_Helper <0x4d, "ds_write_b64", VReg_64>; -defm DS_WRITE2_B64 : DS_Store2_Helper <0x4E, "ds_write2_b64", VReg_64>; -defm DS_WRITE2ST64_B64 : DS_Store2_Helper <0x4f, "ds_write2st64_b64", VReg_64>; +let mayLoad = 0 in { +defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; +defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; +defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; +} defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; @@ -879,9 +887,11 @@ defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmps defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; -defm DS_READ_B64 : DS_Load_Helper <0x76, "ds_read_b64", VReg_64>; -defm DS_READ2_B64 : DS_Load2_Helper <0x77, "ds_read2_b64", VReg_128>; -defm DS_READ2ST64_B64 : DS_Load2_Helper <0x78, "ds_read2st64_b64", VReg_128>; +let mayStore = 0 in { +defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; +defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; +defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; +} defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">;