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Combine several vector-related DAGCombiner tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
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9bb43e1675
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@ -1,17 +0,0 @@
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; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8
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; PR7158
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define arm_aapcs_vfpcc i32 @main() nounwind {
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bb.nph55.bb.nph55.split_crit_edge:
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br label %bb3
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bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
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br i1 undef, label %bb.i19, label %bb3
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bb.i19: ; preds = %bb.i19, %bb3
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%0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3]
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%1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1]
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%2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0]
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%3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0]
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br label %bb.i19
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}
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@ -1,10 +0,0 @@
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; RUN: llc < %s -march=arm -mattr=+neon
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define void @main() nounwind {
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entry:
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store <2 x i64> undef, <2 x i64>* undef, align 16
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%0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
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%1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
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store <16 x i8> %1, <16 x i8>* undef, align 16
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ret void
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}
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@ -1,26 +0,0 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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; converted back to be used as a vector type.
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; CHECK: test:
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define <4 x i32> @test() nounwind {
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entry:
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br i1 undef, label %bb1, label %bb2
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bb1:
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%0 = bitcast <2 x i64> zeroinitializer to <2 x double>
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%1 = extractelement <2 x double> %0, i32 0
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%2 = bitcast double %1 to i64
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%3 = insertelement <1 x i64> undef, i64 %2, i32 0
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; CHECK-NOT: vmov s
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; CHECK: vext.8
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%4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8>
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%5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32>
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br i1 undef, label %bb2, label %bb1
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bb2:
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%result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ]
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ret <4 x i32> %result
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}
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@ -1,8 +0,0 @@
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; RUN: llc < %s -march=arm -mattr=+neon
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define void @lshrIllegalType(<8 x i32>* %A) nounwind {
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%tmp1 = load <8 x i32>* %A
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%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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store <8 x i32> %tmp2, <8 x i32>* %A
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ret void
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}
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63
test/CodeGen/ARM/vector-DAGCombine.ll
Normal file
63
test/CodeGen/ARM/vector-DAGCombine.ll
Normal file
@ -0,0 +1,63 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; PR7158
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define arm_aapcs_vfpcc i32 @test_pr7158() nounwind {
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bb.nph55.bb.nph55.split_crit_edge:
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br label %bb3
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bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
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br i1 undef, label %bb.i19, label %bb3
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bb.i19: ; preds = %bb.i19, %bb3
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%0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3]
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%1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1]
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%2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0]
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%3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0]
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br label %bb.i19
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}
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; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs
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; after legalization.
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define void @test_illegal_build_vector() nounwind {
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entry:
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store <2 x i64> undef, <2 x i64>* undef, align 16
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%0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
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%1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
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store <16 x i8> %1, <16 x i8>* undef, align 16
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ret void
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}
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; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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; converted back to be used as a vector type.
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; CHECK: test_vmovrrd_combine
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define <4 x i32> @test_vmovrrd_combine() nounwind {
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entry:
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br i1 undef, label %bb1, label %bb2
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bb1:
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%0 = bitcast <2 x i64> zeroinitializer to <2 x double>
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%1 = extractelement <2 x double> %0, i32 0
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%2 = bitcast double %1 to i64
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%3 = insertelement <1 x i64> undef, i64 %2, i32 0
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; CHECK-NOT: vmov s
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; CHECK: vext.8
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%4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8>
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%5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32>
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br i1 undef, label %bb2, label %bb1
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bb2:
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%result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ]
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ret <4 x i32> %result
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}
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; Test trying to do a ShiftCombine on illegal types.
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; The vector should be split first.
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define void @lshrIllegalType(<8 x i32>* %A) nounwind {
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%tmp1 = load <8 x i32>* %A
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%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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store <8 x i32> %tmp2, <8 x i32>* %A
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ret void
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}
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