diff --git a/include/llvm/PassManagers.h b/include/llvm/PassManagers.h index 33d101d60d3..498b1626508 100644 --- a/include/llvm/PassManagers.h +++ b/include/llvm/PassManagers.h @@ -13,8 +13,6 @@ #include "llvm/PassManager.h" #include "llvm/ADT/SmallVector.h" -class llvm::PMDataManager; -class llvm::PMStack; //===----------------------------------------------------------------------===// // Overview: diff --git a/lib/Archive/ArchiveWriter.cpp b/lib/Archive/ArchiveWriter.cpp index f5c412609ac..07f7d88dd82 100644 --- a/lib/Archive/ArchiveWriter.cpp +++ b/lib/Archive/ArchiveWriter.cpp @@ -47,11 +47,12 @@ inline unsigned numVbrBytes(unsigned num) { // small ones and four for large ones. We expect this to access file offsets // in the 2^10 to 2^24 range and symbol lengths in the 2^0 to 2^8 range, // so this approach is reasonable. - if (num < 1<<14) + if (num < 1<<14) { if (num < 1<<7) return 1; else return 2; + } if (num < 1<<21) return 3; diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp index b718958f974..7a01a87872b 100644 --- a/lib/CodeGen/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter.cpp @@ -162,11 +162,12 @@ bool AsmPrinter::doFinalization(Module &M) { // If the aliasee has external weak linkage it can be referenced only by // alias itself. In this case it can be not in ExtWeakSymbols list. Emit // weak reference in such case. - if (GV->hasExternalWeakLinkage()) + if (GV->hasExternalWeakLinkage()) { if (TAI->getWeakRefDirective()) O << TAI->getWeakRefDirective() << Target << "\n"; else O << "\t.globl\t" << Target << "\n"; + } } } diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index fb53377b98b..7d7f33e5353 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -278,9 +278,10 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { : BBI.TrueBB->getNumber()) << ") "; RetVal = IfConvertSimple(BBI, Kind); DOUT << (RetVal ? "succeeded!" : "failed!") << "\n"; - if (RetVal) + if (RetVal) { if (isFalse) NumSimpleFalse++; else NumSimple++; + } break; } case ICTriangle: diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index 741c35c43a8..48c25a14a35 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -217,7 +217,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) { // Otherwise, if this range ends in the middle of, or right next to, another // interval, merge it into that interval. - if (it != ranges.end()) + if (it != ranges.end()) { if (LR.valno == it->valno) { if (it->start <= End) { it = extendIntervalStartTo(it, Start); @@ -237,6 +237,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) { assert(it->start >= End && "Cannot overlap two LiveRanges with differing ValID's"); } + } // Otherwise, this is just a new range that doesn't interact with anything. // Insert it. diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index f29b45eb142..38fb5e6894d 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -695,7 +695,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // Unallocatable register dead, ignore. continue; } else { - assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 && + assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) && "Silently clearing a virtual register?"); } @@ -832,11 +832,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // Spill all physical registers holding virtual registers now. for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) - if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) { if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); else removePhysReg(i); + } } /// runOnMachineFunction - Register allocate the whole function diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 026666c45fc..cd57d3ad369 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1996,11 +1996,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { LHSShiftAmt == RHSShiftAmt.getOperand(1)) { if (ConstantSDNode *SUBC = dyn_cast(RHSShiftAmt.getOperand(0))) { - if (SUBC->getValue() == OpSizeInBits) + if (SUBC->getValue() == OpSizeInBits) { if (HasROTL) return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; else return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; + } } } @@ -2010,11 +2011,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { RHSShiftAmt == LHSShiftAmt.getOperand(1)) { if (ConstantSDNode *SUBC = dyn_cast(LHSShiftAmt.getOperand(0))) { - if (SUBC->getValue() == OpSizeInBits) + if (SUBC->getValue() == OpSizeInBits) { if (HasROTL) return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; else return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; + } } } @@ -2230,7 +2232,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { // the constant which would cause it to be modified for this // operation. if (N->getOpcode() == ISD::SRA) { - uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; + uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1); if ((bool)BinOpRHSSign != HighBitSet) return SDOperand(); } @@ -2552,7 +2554,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) { return SDOperand(N, 0); // Don't revisit N. // fold selects based on a setcc into other things, such as min/max/abs - if (N0.getOpcode() == ISD::SETCC) + if (N0.getOpcode() == ISD::SETCC) { // FIXME: // Check against MVT::Other for SELECT_CC, which is a workaround for targets // having to say they don't support SELECT_CC on every type the DAG knows @@ -2562,6 +2564,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) { N1, N2, N0.getOperand(2)); else return SimplifySelect(N0, N1, N2); + } return SDOperand(); } @@ -4013,8 +4016,8 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { if (!((Use->getOpcode() == ISD::LOAD && cast(Use)->getBasePtr() == Ptr) || - (Use->getOpcode() == ISD::STORE) && - cast(Use)->getBasePtr() == Ptr)) + (Use->getOpcode() == ISD::STORE && + cast(Use)->getBasePtr() == Ptr))) RealUse = true; } if (!RealUse) @@ -4131,8 +4134,8 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { SDNode *UseUse = *III; if (!((UseUse->getOpcode() == ISD::LOAD && cast(UseUse)->getBasePtr().Val == Use) || - (UseUse->getOpcode() == ISD::STORE) && - cast(UseUse)->getBasePtr().Val == Use)) + (UseUse->getOpcode() == ISD::STORE && + cast(UseUse)->getBasePtr().Val == Use))) RealUse = true; } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 2cda59758ce..17aaa75c9ee 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1269,15 +1269,18 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { unsigned RScratch = calcMaxScratches(right); if (LScratch > RScratch) return true; - else if (LScratch == RScratch) + else if (LScratch == RScratch) { if (left->Height > right->Height) return true; - else if (left->Height == right->Height) + else if (left->Height == right->Height) { if (left->Depth < right->Depth) return true; - else if (left->Depth == right->Depth) + else if (left->Depth == right->Depth) { if (left->CycleBound > right->CycleBound) return true; + } + } + } } } return false; @@ -1509,15 +1512,19 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { if (LPriority+LBonus < RPriority+RBonus) return true; - else if (LPriority == RPriority) + else if (LPriority == RPriority) { if (left->Depth < right->Depth) return true; - else if (left->Depth == right->Depth) + else if (left->Depth == right->Depth) { if (left->NumSuccsLeft > right->NumSuccsLeft) return true; - else if (left->NumSuccsLeft == right->NumSuccsLeft) + else if (left->NumSuccsLeft == right->NumSuccsLeft) { if (left->CycleBound > right->CycleBound) return true; + } + } + } + return false; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index eb3729c813f..8a2962f0c33 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1075,7 +1075,7 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1, } } } - if (ConstantFPSDNode *N1C = dyn_cast(N1.Val)) + if (ConstantFPSDNode *N1C = dyn_cast(N1.Val)) { if (ConstantFPSDNode *N2C = dyn_cast(N2.Val)) { // No compile time operations on this type yet. if (N1C->getValueType(0) == MVT::ppcf128) @@ -1127,7 +1127,8 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1, // Ensure that the constant occurs on the RHS. return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); } - + } + // Could not fold it. return SDOperand(); } @@ -2334,20 +2335,22 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, break; } case ISD::SELECT: - if (N1C) - if (N1C->getValue()) + if (N1C) { + if (N1C->getValue()) return N2; // select true, X, Y -> X else return N3; // select false, X, Y -> Y + } if (N2 == N3) return N2; // select C, X, X -> X break; case ISD::BRCOND: - if (N2C) + if (N2C) { if (N2C->getValue()) // Unconditional branch return getNode(ISD::BR, MVT::Other, N1, N3); else return N1; // Never-taken branch + } break; case ISD::VECTOR_SHUFFLE: assert(VT == N1.getValueType() && VT == N2.getValueType() && diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 1ee93d7bba1..001c9f6c533 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2602,7 +2602,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, static GlobalVariable *ExtractTypeInfo (Value *V) { V = IntrinsicInst::StripPointerCasts(V); GlobalVariable *GV = dyn_cast(V); - assert (GV || isa(V) && + assert ((GV || isa(V)) && "TypeInfo must be a global variable or NULL"); return GV; } diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 253d5c16ffa..e93bac4987c 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -191,7 +191,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { MachineInstr &MI = *MII; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); - if (MO.isRegister() && MO.getReg()) + if (MO.isRegister() && MO.getReg()) { if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM.getPhys(VirtReg); @@ -220,6 +220,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { } else { MF.getRegInfo().setPhysRegUsed(MO.getReg()); } + } } DOUT << '\t' << MI; diff --git a/lib/ExecutionEngine/Interpreter/Execution.cpp b/lib/ExecutionEngine/Interpreter/Execution.cpp index 3463edc5c45..0d9959a40bc 100644 --- a/lib/ExecutionEngine/Interpreter/Execution.cpp +++ b/lib/ExecutionEngine/Interpreter/Execution.cpp @@ -385,16 +385,16 @@ static GenericValue executeFCMP_OGT(GenericValue Src1, GenericValue Src2, return Dest; } -#define IMPLEMENT_UNORDERED(TY, X,Y) \ - if (TY == Type::FloatTy) \ - if (X.FloatVal != X.FloatVal || Y.FloatVal != Y.FloatVal) { \ - Dest.IntVal = APInt(1,true); \ - return Dest; \ - } \ - else if (X.DoubleVal != X.DoubleVal || Y.DoubleVal != Y.DoubleVal) { \ - Dest.IntVal = APInt(1,true); \ - return Dest; \ - } +#define IMPLEMENT_UNORDERED(TY, X,Y) \ + if (TY == Type::FloatTy) { \ + if (X.FloatVal != X.FloatVal || Y.FloatVal != Y.FloatVal) { \ + Dest.IntVal = APInt(1,true); \ + return Dest; \ + } \ + } else if (X.DoubleVal != X.DoubleVal || Y.DoubleVal != Y.DoubleVal) { \ + Dest.IntVal = APInt(1,true); \ + return Dest; \ + } static GenericValue executeFCMP_UEQ(GenericValue Src1, GenericValue Src2, @@ -901,11 +901,12 @@ void Interpreter::visitCallSite(CallSite CS) { // We do this by zero or sign extending the value as appropriate // according to the parameter attributes const Type *Ty = V->getType(); - if (Ty->isInteger() && (ArgVals.back().IntVal.getBitWidth() < 32)) + if (Ty->isInteger() && (ArgVals.back().IntVal.getBitWidth() < 32)) { if (CS.paramHasAttr(pNum, ParamAttr::ZExt)) ArgVals.back().IntVal = ArgVals.back().IntVal.zext(32); else if (CS.paramHasAttr(pNum, ParamAttr::SExt)) ArgVals.back().IntVal = ArgVals.back().IntVal.sext(32); + } } // To handle indirect calls, we must get the pointer value from the argument