misched preparation: modularize schedule verification.

ScheduleDAG will not refer to the scheduled instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-03-07 05:21:36 +00:00
parent dbdca36af8
commit 4c72720427
8 changed files with 37 additions and 17 deletions

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@ -543,9 +543,9 @@ namespace llvm {
virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
#ifndef NDEBUG
/// VerifySchedule - Verify that all SUnits were scheduled and that
/// their state is consistent.
void VerifySchedule(bool isBottomUp);
/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
/// their state is consistent. Return the number of scheduled SUnits.
unsigned VerifyScheduledDAG(bool isBottomUp);
#endif
protected:

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@ -703,6 +703,12 @@ void SchedulePostRATDList::ListScheduleTopDown() {
}
#ifndef NDEBUG
VerifySchedule(/*isBottomUp=*/false);
#endif
unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
unsigned Noops = 0;
for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
if (!Sequence[i])
++Noops;
assert(Sequence.size() - Noops == ScheduledNodes &&
"The number of nodes scheduled doesn't match the expected number!");
#endif // NDEBUG
}

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@ -346,13 +346,12 @@ void SUnit::dumpAll(const ScheduleDAG *G) const {
}
#ifndef NDEBUG
/// VerifySchedule - Verify that all SUnits were scheduled and that
/// their state is consistent.
/// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
/// their state is consistent. Return the number of scheduled nodes.
///
void ScheduleDAG::VerifySchedule(bool isBottomUp) {
unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) {
bool AnyNotSched = false;
unsigned DeadNodes = 0;
unsigned Noops = 0;
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
if (!SUnits[i].isScheduled) {
if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
@ -393,12 +392,8 @@ void ScheduleDAG::VerifySchedule(bool isBottomUp) {
}
}
}
for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
if (!Sequence[i])
++Noops;
assert(!AnyNotSched);
assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
"The number of nodes scheduled doesn't match the expected number!");
return SUnits.size() - DeadNodes;
}
#endif

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@ -630,7 +630,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
std::reverse(Sequence.begin(), Sequence.end());
#ifndef NDEBUG
VerifySchedule(/*isBottomUp=*/true);
VerifyScheduledSequence(/*isBottomUp=*/true);
#endif
}

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@ -1475,7 +1475,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
std::reverse(Sequence.begin(), Sequence.end());
#ifndef NDEBUG
VerifySchedule(/*isBottomUp=*/true);
VerifyScheduledSequence(/*isBottomUp=*/true);
#endif
}

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@ -621,6 +621,21 @@ void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
}
}
#ifndef NDEBUG
/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
/// their state is consistent with the nodes listed in Sequence.
///
void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
unsigned Noops = 0;
for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
if (!Sequence[i])
++Noops;
assert(Sequence.size() - Noops == ScheduledNodes &&
"The number of nodes scheduled doesn't match the expected number!");
}
#endif // NDEBUG
namespace {
struct OrderSorter {
bool operator()(const std::pair<unsigned, MachineInstr*> &A,

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@ -111,6 +111,10 @@ namespace llvm {
///
virtual void Schedule() = 0;
/// VerifyScheduledSequence - Verify that all SUnits are scheduled and
/// consistent with the Sequence of scheduled instructions.
void VerifyScheduledSequence(bool isBottomUp);
virtual void dumpNode(const SUnit *SU) const;
virtual std::string getGraphNodeLabel(const SUnit *SU) const;

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@ -261,7 +261,7 @@ void ScheduleDAGVLIW::listScheduleTopDown() {
}
#ifndef NDEBUG
VerifySchedule(/*isBottomUp=*/false);
VerifyScheduledSequence(/*isBottomUp=*/false);
#endif
}