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Add several new instructions supported by the latest MicroBlaze.
These instructions are not generated by the backend yet, this will come in a later commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145161 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -123,6 +123,7 @@ static unsigned decodeSEXT(uint32_t insn) {
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case 0x41: return MBlaze::SRL;
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case 0x21: return MBlaze::SRC;
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case 0x01: return MBlaze::SRA;
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case 0xE0: return MBlaze::CLZ;
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}
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}
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@ -176,6 +177,13 @@ static unsigned decodeBR(uint32_t insn) {
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}
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static unsigned decodeBRI(uint32_t insn) {
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switch (insn&0x3FFFFFF) {
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default: break;
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case 0x0020004: return MBlaze::IDMEMBAR;
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case 0x0220004: return MBlaze::DMEMBAR;
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case 0x0420004: return MBlaze::IMEMBAR;
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}
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switch ((insn>>16)&0x1F) {
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default: return UNSUPPORTED;
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case 0x00: return MBlaze::BRI;
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@ -531,6 +539,9 @@ MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
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default:
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return Fail;
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case MBlazeII::FC:
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break;
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case MBlazeII::FRRRR:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
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return Fail;
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@ -547,6 +558,13 @@ MCDisassembler::DecodeStatus MBlazeDisassembler::getInstruction(MCInst &instr,
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instr.addOperand(MCOperand::CreateReg(RB));
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break;
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case MBlazeII::FRR:
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if (RD == UNSUPPORTED || RA == UNSUPPORTED)
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return Fail;
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instr.addOperand(MCOperand::CreateReg(RD));
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instr.addOperand(MCOperand::CreateReg(RA));
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break;
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case MBlazeII::FRI:
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switch (opcode) {
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default:
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@ -35,6 +35,7 @@ def FRIR : Format<17>; // RSUBI
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def FRRRR : Format<18>; // RSUB, FRSUB
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def FRI : Format<19>; // RSUB, FRSUB
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def FC : Format<20>; // NOP
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def FRR : Format<21>; // CLZ
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//===----------------------------------------------------------------------===//
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// Describe MBlaze instructions format
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@ -202,3 +203,26 @@ class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
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let Inst{11-16} = flags;
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let Inst{17-31} = imm15;
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}
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//===----------------------------------------------------------------------===//
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// TCLZ instruction class in MBlaze : <|opcode|rd|imm15|>
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//===----------------------------------------------------------------------===//
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class TCLZ<bits<6> op, bits<16> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op, FRR, outs, ins, asmstr, pattern, itin> {
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bits<5> rd;
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bits<5> ra;
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let Inst{6-10} = rd;
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let Inst{11-15} = ra;
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let Inst{16-31} = flags;
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}
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//===----------------------------------------------------------------------===//
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// MBAR instruction class in MBlaze : <|opcode|rd|imm15|>
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//===----------------------------------------------------------------------===//
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class MBAR<bits<6> op, bits<26> flags, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin> :
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MBlazeInst<op, FC, outs, ins, asmstr, pattern, itin> {
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let Inst{6-31} = flags;
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}
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@ -597,6 +597,15 @@ let neverHasSideEffects = 1 in {
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def NOP : MBlazeInst<0x20, FC, (outs), (ins), "nop ", [], IIC_ALU>;
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}
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let Predicates=[HasPatCmp] in {
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def CLZ : TCLZ<0x24, 0x00E0, (outs GPR:$dst), (ins GPR:$src),
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"clz $dst, $src", [], IIC_ALU>;
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}
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def IMEMBAR : MBAR<0x2E, 0x0420004, (outs), (ins), "mbar 2", [], IIC_ALU>;
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def DMEMBAR : MBAR<0x2E, 0x0220004, (outs), (ins), "mbar 1", [], IIC_ALU>;
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def IDMEMBAR : MBAR<0x2E, 0x0020004, (outs), (ins), "mbar 0", [], IIC_ALU>;
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let usesCustomInserter = 1 in {
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def Select_CC : MBlazePseudo<(outs GPR:$dst),
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(ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), // F T reversed
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@ -51,6 +51,7 @@ namespace MBlazeII {
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FRRRR,
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FRI,
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FC,
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FRR,
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FormMask = 63
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//===------------------------------------------------------------------===//
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14
test/MC/Disassembler/MBlaze/mblaze_mbar.txt
Normal file
14
test/MC/Disassembler/MBlaze/mblaze_mbar.txt
Normal file
@ -0,0 +1,14 @@
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# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
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################################################################################
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# Memory Barrier instructions
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################################################################################
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# CHECK: mbar 0
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0xB8 0x02 0x00 0x04
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# CHECK: mbar 1
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0xB8 0x22 0x00 0x04
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# CHECK: mbar 2
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0xB8 0x42 0x00 0x04
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@ -12,3 +12,6 @@
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# CHECK: pcmpeq r0, r1, r2
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0x88 0x01 0x14 0x00
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# CHECK: clz r0, r1
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0x90 0x01 0x00 0xE0
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