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Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8,12 +8,12 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMPowerPC
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TARGET = PowerPC PPC32
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TARGET = PPC
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
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PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
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PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc \
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PPC32GenInstrInfo.inc PPC32GenDAGISel.inc
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BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
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PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
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PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
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PPCGenInstrInfo.inc PPCGenDAGISel.inc
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include $(LEVEL)/Makefile.common
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@ -42,10 +42,10 @@ extern PPCTargetEnum PPCTarget;
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// Defines symbolic names for PowerPC registers. This defines a mapping from
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// register name to register number.
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//
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#include "PowerPCGenRegisterNames.inc"
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#include "PPCGenRegisterNames.inc"
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// Defines symbolic names for the PowerPC instructions.
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//
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#include "PowerPCGenInstrNames.inc"
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#include "PPCGenInstrNames.inc"
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#endif
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38
lib/Target/PowerPC/PPC.td
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38
lib/Target/PowerPC/PPC.td
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@ -0,0 +1,38 @@
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//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PowerPCRegisterInfo.td"
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include "PowerPCInstrInfo.td"
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def PPC : Target {
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// Pointers on PPC are 32-bits in size.
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let PointerType = i32;
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// According to the Mach-O Runtime ABI, these regs are nonvolatile across
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// calls
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let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
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F30, F31, CR2, CR3, CR4, LR];
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// Pull in Instruction Info:
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let InstructionSet = PowerPCInstrInfo;
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}
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@ -1,4 +1,4 @@
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//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
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//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -43,10 +43,10 @@ using namespace llvm;
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namespace {
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Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
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struct PowerPCAsmPrinter : public AsmPrinter {
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struct PPCAsmPrinter : public AsmPrinter {
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std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
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PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM)
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PPCAsmPrinter(std::ostream &O, TargetMachine &TM)
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: AsmPrinter(O, TM), LabelNumber(0) {}
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/// Unique incrementer for label values for referencing Global values.
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@ -175,10 +175,10 @@ namespace {
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/// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
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/// X
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///
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struct DarwinAsmPrinter : public PowerPCAsmPrinter {
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struct DarwinAsmPrinter : public PPCAsmPrinter {
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DarwinAsmPrinter(std::ostream &O, TargetMachine &TM)
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: PowerPCAsmPrinter(O, TM) {
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: PPCAsmPrinter(O, TM) {
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CommentString = ";";
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GlobalPrefix = "_";
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ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
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@ -198,13 +198,13 @@ namespace {
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/// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
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///
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struct AIXAsmPrinter : public PowerPCAsmPrinter {
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struct AIXAsmPrinter : public PPCAsmPrinter {
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/// Map for labels corresponding to global variables
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///
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std::map<const GlobalVariable*,std::string> GVToLabelMap;
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AIXAsmPrinter(std::ostream &O, TargetMachine &TM)
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: PowerPCAsmPrinter(O, TM) {
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: PPCAsmPrinter(O, TM) {
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CommentString = "#";
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GlobalPrefix = "_";
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ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
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@ -252,9 +252,9 @@ FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
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}
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// Include the auto-generated portion of the assembly writer
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#include "PowerPCGenAsmWriter.inc"
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#include "PPCGenAsmWriter.inc"
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void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
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void PPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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int new_symbol;
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@ -340,7 +340,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
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/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
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/// the current output stream.
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///
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void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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// Check for slwi/srwi mnemonics.
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@ -1,4 +1,4 @@
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//===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
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//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -24,7 +24,7 @@
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using namespace llvm;
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namespace {
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class PPC32CodeEmitter : public MachineFunctionPass {
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class PPCCodeEmitter : public MachineFunctionPass {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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@ -38,7 +38,7 @@ namespace {
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int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
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public:
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PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
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PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
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: TM(T), MCE(M) {}
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const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
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@ -76,13 +76,13 @@ namespace {
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bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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// Machine code emitter pass for PowerPC
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PM.add(new PPC32CodeEmitter(*this, MCE));
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PM.add(new PPCCodeEmitter(*this, MCE));
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// Delete machine code for this function after emitting it
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PM.add(createMachineCodeDeleter());
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return false;
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}
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bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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MCE.startFunction(MF);
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MCE.emitConstantPool(MF.getConstantPool());
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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@ -114,7 +114,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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assert(!PICEnabled && "CodeEmitter does not support PIC!");
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BBLocations[&MBB] = MCE.getCurrentPCValue();
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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}
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}
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int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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int rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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@ -260,5 +260,5 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
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return rv;
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}
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#include "PPC32GenCodeEmitter.inc"
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#include "PPCGenCodeEmitter.inc"
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}
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// Include the pieces autogenerated from the target description.
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#include "PPC32GenDAGISel.inc"
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#include "PPCGenDAGISel.inc"
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private:
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SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
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//===----------------------------------------------------------------------===//
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#include "PPC32InstrInfo.h"
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#include "PPC32GenInstrInfo.inc"
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#include "PPCGenInstrInfo.inc"
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#include "PowerPC.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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PPC32InstrInfo::PPC32InstrInfo()
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: TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {}
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: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
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bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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using namespace llvm;
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PPC32RegisterInfo::PPC32RegisterInfo()
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: PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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@ -342,5 +342,5 @@ void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
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}
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}
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#include "PPC32GenRegisterInfo.inc"
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#include "PPCGenRegisterInfo.inc"
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#define POWERPC32_REGISTERINFO_H
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#include "PowerPC.h"
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#include "PPC32GenRegisterInfo.h.inc"
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#include "PPCGenRegisterInfo.h.inc"
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#include <map>
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namespace llvm {
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class Type;
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class PPC32RegisterInfo : public PPC32GenRegisterInfo {
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class PPC32RegisterInfo : public PPCGenRegisterInfo {
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std::map<unsigned, unsigned> ImmToIdxMap;
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public:
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PPC32RegisterInfo();
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