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Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-14 23:37:35 +00:00
parent e87bc1f3a8
commit 4c7b43b43f
9 changed files with 70 additions and 32 deletions
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10
lib/Target/PowerPC/Makefile
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@ -8,12 +8,12 @@
##===----------------------------------------------------------------------===## ##===----------------------------------------------------------------------===##
LEVEL = ../../.. LEVEL = ../../..
LIBRARYNAME = LLVMPowerPC LIBRARYNAME = LLVMPowerPC
TARGET = PowerPC PPC32 TARGET = PPC
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \ BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc \ PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
PPC32GenInstrInfo.inc PPC32GenDAGISel.inc PPCGenInstrInfo.inc PPCGenDAGISel.inc
include $(LEVEL)/Makefile.common include $(LEVEL)/Makefile.common

4
lib/Target/PowerPC/PPC.h
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@ -42,10 +42,10 @@ extern PPCTargetEnum PPCTarget;
// Defines symbolic names for PowerPC registers. This defines a mapping from // Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "PowerPCGenRegisterNames.inc" #include "PPCGenRegisterNames.inc"
// Defines symbolic names for the PowerPC instructions. // Defines symbolic names for the PowerPC instructions.
// //
#include "PowerPCGenInstrNames.inc" #include "PPCGenInstrNames.inc"
#endif #endif

38
lib/Target/PowerPC/PPC.td Normal file
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@ -0,0 +1,38 @@
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the PowerPC target.
//
//===----------------------------------------------------------------------===//
// Get the target-independent interfaces which we are implementing.
//
include "../Target.td"
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "PowerPCRegisterInfo.td"
include "PowerPCInstrInfo.td"
def PPC : Target {
// Pointers on PPC are 32-bits in size.
let PointerType = i32;
// According to the Mach-O Runtime ABI, these regs are nonvolatile across
// calls
let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
F30, F31, CR2, CR3, CR4, LR];
// Pull in Instruction Info:
let InstructionSet = PowerPCInstrInfo;
}

20
lib/Target/PowerPC/PPCAsmPrinter.cpp
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@ -1,4 +1,4 @@
//===-- PowerPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===// //===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -43,10 +43,10 @@ using namespace llvm;
namespace { namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
struct PowerPCAsmPrinter : public AsmPrinter { struct PPCAsmPrinter : public AsmPrinter {
std::set<std::string> FnStubs, GVStubs, LinkOnceStubs; std::set<std::string> FnStubs, GVStubs, LinkOnceStubs;
PowerPCAsmPrinter(std::ostream &O, TargetMachine &TM) PPCAsmPrinter(std::ostream &O, TargetMachine &TM)
: AsmPrinter(O, TM), LabelNumber(0) {} : AsmPrinter(O, TM), LabelNumber(0) {}
/// Unique incrementer for label values for referencing Global values. /// Unique incrementer for label values for referencing Global values.
@ -175,10 +175,10 @@ namespace {
/// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS /// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
/// X /// X
/// ///
struct DarwinAsmPrinter : public PowerPCAsmPrinter { struct DarwinAsmPrinter : public PPCAsmPrinter {
DarwinAsmPrinter(std::ostream &O, TargetMachine &TM) DarwinAsmPrinter(std::ostream &O, TargetMachine &TM)
: PowerPCAsmPrinter(O, TM) { : PPCAsmPrinter(O, TM) {
CommentString = ";"; CommentString = ";";
GlobalPrefix = "_"; GlobalPrefix = "_";
ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
@ -198,13 +198,13 @@ namespace {
/// AIXAsmPrinter - PowerPC assembly printer, customized for AIX /// AIXAsmPrinter - PowerPC assembly printer, customized for AIX
/// ///
struct AIXAsmPrinter : public PowerPCAsmPrinter { struct AIXAsmPrinter : public PPCAsmPrinter {
/// Map for labels corresponding to global variables /// Map for labels corresponding to global variables
/// ///
std::map<const GlobalVariable*,std::string> GVToLabelMap; std::map<const GlobalVariable*,std::string> GVToLabelMap;
AIXAsmPrinter(std::ostream &O, TargetMachine &TM) AIXAsmPrinter(std::ostream &O, TargetMachine &TM)
: PowerPCAsmPrinter(O, TM) { : PPCAsmPrinter(O, TM) {
CommentString = "#"; CommentString = "#";
GlobalPrefix = "_"; GlobalPrefix = "_";
ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
@ -252,9 +252,9 @@ FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
} }
// Include the auto-generated portion of the assembly writer // Include the auto-generated portion of the assembly writer
#include "PowerPCGenAsmWriter.inc" #include "PPCGenAsmWriter.inc"
void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { void PPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
const MRegisterInfo &RI = *TM.getRegisterInfo(); const MRegisterInfo &RI = *TM.getRegisterInfo();
int new_symbol; int new_symbol;
@ -340,7 +340,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to /// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream. /// the current output stream.
/// ///
void PowerPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) { void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts; ++EmittedInsts;
// Check for slwi/srwi mnemonics. // Check for slwi/srwi mnemonics.

16
lib/Target/PowerPC/PPCCodeEmitter.cpp
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@ -1,4 +1,4 @@
//===-- PPC32CodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=// //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -----*- C++ -*-=//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -24,7 +24,7 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
class PPC32CodeEmitter : public MachineFunctionPass { class PPCCodeEmitter : public MachineFunctionPass {
TargetMachine &TM; TargetMachine &TM;
MachineCodeEmitter &MCE; MachineCodeEmitter &MCE;
@ -38,7 +38,7 @@ namespace {
int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
public: public:
PPC32CodeEmitter(TargetMachine &T, MachineCodeEmitter &M) PPCCodeEmitter(TargetMachine &T, MachineCodeEmitter &M)
: TM(T), MCE(M) {} : TM(T), MCE(M) {}
const char *getPassName() const { return "PowerPC Machine Code Emitter"; } const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@ -76,13 +76,13 @@ namespace {
bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, bool PPC32TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) { MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC // Machine code emitter pass for PowerPC
PM.add(new PPC32CodeEmitter(*this, MCE)); PM.add(new PPCCodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it // Delete machine code for this function after emitting it
PM.add(createMachineCodeDeleter()); PM.add(createMachineCodeDeleter());
return false; return false;
} }
bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) { bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
MCE.startFunction(MF); MCE.startFunction(MF);
MCE.emitConstantPool(MF.getConstantPool()); MCE.emitConstantPool(MF.getConstantPool());
for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
@ -114,7 +114,7 @@ bool PPC32CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
return false; return false;
} }
void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
assert(!PICEnabled && "CodeEmitter does not support PIC!"); assert(!PICEnabled && "CodeEmitter does not support PIC!");
BBLocations[&MBB] = MCE.getCurrentPCValue(); BBLocations[&MBB] = MCE.getCurrentPCValue();
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
@ -175,7 +175,7 @@ static unsigned enumRegToMachineReg(unsigned enumReg) {
} }
} }
int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
int rv = 0; // Return value; defaults to 0 for unhandled cases int rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT. // or things that get fixed up later by the JIT.
@ -260,5 +260,5 @@ int PPC32CodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
return rv; return rv;
} }
#include "PPC32GenCodeEmitter.inc" #include "PPCGenCodeEmitter.inc"

2
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -90,7 +90,7 @@ namespace {
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "PPC32GenDAGISel.inc" #include "PPCGenDAGISel.inc"
private: private:
SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op); SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);

4
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -12,14 +12,14 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PPC32InstrInfo.h" #include "PPC32InstrInfo.h"
#include "PPC32GenInstrInfo.inc" #include "PPCGenInstrInfo.inc"
#include "PowerPC.h" #include "PowerPC.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include <iostream> #include <iostream>
using namespace llvm; using namespace llvm;
PPC32InstrInfo::PPC32InstrInfo() PPC32InstrInfo::PPC32InstrInfo()
: TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {} : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI, bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg, unsigned& sourceReg,

4
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@ -32,7 +32,7 @@
using namespace llvm; using namespace llvm;
PPC32RegisterInfo::PPC32RegisterInfo() PPC32RegisterInfo::PPC32RegisterInfo()
: PPC32GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
@ -342,5 +342,5 @@ void PPC32RegisterInfo::emitEpilogue(MachineFunction &MF,
} }
} }
#include "PPC32GenRegisterInfo.inc" #include "PPCGenRegisterInfo.inc"

4
lib/Target/PowerPC/PPCRegisterInfo.h
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@ -15,14 +15,14 @@
#define POWERPC32_REGISTERINFO_H #define POWERPC32_REGISTERINFO_H
#include "PowerPC.h" #include "PowerPC.h"
#include "PPC32GenRegisterInfo.h.inc" #include "PPCGenRegisterInfo.h.inc"
#include <map> #include <map>
namespace llvm { namespace llvm {
class Type; class Type;
class PPC32RegisterInfo : public PPC32GenRegisterInfo { class PPC32RegisterInfo : public PPCGenRegisterInfo {
std::map<unsigned, unsigned> ImmToIdxMap; std::map<unsigned, unsigned> ImmToIdxMap;
public: public:
PPC32RegisterInfo(); PPC32RegisterInfo();