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ARM assembly parsing and encoding for four-register VST1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-29 22:58:48 +00:00
parent 2662c83a59
commit 4c7edb3ad8
5 changed files with 53 additions and 52 deletions
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8
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -267,8 +267,9 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,true},
{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, true, SingleSpc, 4, 1 ,true},
{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
@ -1205,7 +1206,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case ARM::VST4d8Pseudo_UPD:
case ARM::VST4d16Pseudo_UPD:
case ARM::VST4d32Pseudo_UPD:
case ARM::VST1d64QPseudo_UPD:
case ARM::VST1d64QPseudoWB_fixed:
case ARM::VST1d64QPseudoWB_register:
case ARM::VST4q8Pseudo_UPD:
case ARM::VST4q16Pseudo_UPD:
case ARM::VST4q32Pseudo_UPD:

3
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1580,6 +1580,7 @@ static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
}
return Opc; // If not one we handle, return it unchanged.
}
@ -2898,7 +2899,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case ARMISD::VST4_UPD: {
unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
ARM::VST4d32Pseudo_UPD,ARM::VST1d64QPseudoWB_fixed};
unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
ARM::VST4q16Pseudo_UPD,
ARM::VST4q32Pseudo_UPD };

52
lib/Target/ARM/ARMInstrNEON.td
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@ -1373,35 +1373,47 @@ def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
// ...with 4 registers
class VST1D4<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0010, op7_4, (outs),
(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
(ins addrmode6:$Rn, VecListFourD:$Vd),
IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
[]> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
}
class VST1D4WB<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm,
DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
"vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
multiclass VST1D4WB<bits<4> op7_4, string Dt> {
def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
"vst1", Dt, "$Vd, $Rn!",
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
let AsmMatchConverter = "cvtVSTwbFixed";
}
def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
(ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
IIC_VLD1x4u,
"vst1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVSTInstruction";
let AsmMatchConverter = "cvtVSTwbRegister";
}
}
def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>

36
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2204,10 +2204,14 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::VST1d16Twb_register:
case ARM::VST1d32Twb_register:
case ARM::VST1d64Twb_register:
case ARM::VST1d8Q_UPD:
case ARM::VST1d16Q_UPD:
case ARM::VST1d32Q_UPD:
case ARM::VST1d64Q_UPD:
case ARM::VST1d8Qwb_fixed:
case ARM::VST1d16Qwb_fixed:
case ARM::VST1d32Qwb_fixed:
case ARM::VST1d64Qwb_fixed:
case ARM::VST1d8Qwb_register:
case ARM::VST1d16Qwb_register:
case ARM::VST1d32Qwb_register:
case ARM::VST1d64Qwb_register:
case ARM::VST2d8_UPD:
case ARM::VST2d16_UPD:
case ARM::VST2d32_UPD:
@ -2268,14 +2272,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second input register
switch (Inst.getOpcode()) {
case ARM::VST1d8Q:
case ARM::VST1d16Q:
case ARM::VST1d32Q:
case ARM::VST1d64Q:
case ARM::VST1d8Q_UPD:
case ARM::VST1d16Q_UPD:
case ARM::VST1d32Q_UPD:
case ARM::VST1d64Q_UPD:
case ARM::VST2d8:
case ARM::VST2d16:
case ARM::VST2d32:
@ -2330,14 +2326,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Third input register
switch (Inst.getOpcode()) {
case ARM::VST1d8Q:
case ARM::VST1d16Q:
case ARM::VST1d32Q:
case ARM::VST1d64Q:
case ARM::VST1d8Q_UPD:
case ARM::VST1d16Q_UPD:
case ARM::VST1d32Q_UPD:
case ARM::VST1d64Q_UPD:
case ARM::VST2q8:
case ARM::VST2q16:
case ARM::VST2q32:
@ -2380,14 +2368,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Fourth input register
switch (Inst.getOpcode()) {
case ARM::VST1d8Q:
case ARM::VST1d16Q:
case ARM::VST1d32Q:
case ARM::VST1d64Q:
case ARM::VST1d8Q_UPD:
case ARM::VST1d16Q_UPD:
case ARM::VST1d32Q_UPD:
case ARM::VST1d64Q_UPD:
case ARM::VST2q8:
case ARM::VST2q16:
case ARM::VST2q32:

6
test/MC/ARM/neon-vst-encoding.s
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@ -11,6 +11,9 @@
vst1.8 {d16, d17, d18}, [r0, :64]
vst1.8 {d16, d17, d18}, [r0, :64]!
vst1.8 {d16, d17, d18}, [r0], r3
vst1.8 {d16, d17, d18, d19}, [r0, :64]
vst1.16 {d16, d17, d18, d19}, [r1, :64]!
vst1.64 {d16, d17, d18, d19}, [r3], r2
@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4]
@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4]
@ -23,6 +26,9 @@
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4]
@ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4]
@ vst2.8 {d16, d17}, [r0, :64]