mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
PTX: Continue to fix up the register mess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
e37a83f66b
commit
4c7ffb6a7e
@ -39,32 +39,45 @@ StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const {
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void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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// Decode the register number into type and offset
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unsigned RegType = RegNo & 0xF;
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unsigned RegOffset = RegNo >> 4;
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unsigned RegSpace = RegNo & 0x7;
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unsigned RegType = (RegNo >> 3) & 0x7;
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unsigned RegOffset = RegNo >> 6;
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// Print the register
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OS << "%";
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switch (RegType) {
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switch (RegSpace) {
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default:
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llvm_unreachable("Unknown register type!");
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case PTXRegisterType::Pred:
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OS << "p";
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llvm_unreachable("Unknown register space!");
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case PTXRegisterSpace::Reg:
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switch (RegType) {
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default:
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llvm_unreachable("Unknown register type!");
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case PTXRegisterType::Pred:
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OS << "p";
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break;
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case PTXRegisterType::B16:
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OS << "rh";
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break;
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case PTXRegisterType::B32:
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OS << "r";
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break;
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case PTXRegisterType::B64:
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OS << "rd";
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break;
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case PTXRegisterType::F32:
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OS << "f";
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break;
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case PTXRegisterType::F64:
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OS << "fd";
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break;
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}
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break;
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case PTXRegisterType::B16:
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OS << "rh";
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case PTXRegisterSpace::Return:
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OS << "ret";
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break;
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case PTXRegisterType::B32:
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OS << "r";
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break;
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case PTXRegisterType::B64:
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OS << "rd";
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break;
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case PTXRegisterType::F32:
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OS << "f";
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break;
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case PTXRegisterType::F64:
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OS << "fd";
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case PTXRegisterSpace::Argument:
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OS << "arg";
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break;
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}
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@ -17,6 +17,8 @@
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#ifndef PTXBASEINFO_H
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#define PTXBASEINFO_H
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "PTXMCTargetDesc.h"
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namespace llvm {
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@ -69,6 +71,63 @@ namespace llvm {
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F64
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};
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} // namespace PTXRegisterType
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namespace PTXRegisterSpace {
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// Register space encoded in MCOperands
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enum {
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Reg = 0,
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Local,
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Param,
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Argument,
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Return
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};
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}
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inline static void decodeRegisterName(raw_ostream &OS,
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unsigned EncodedReg) {
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OS << "%";
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unsigned RegSpace = EncodedReg & 0x7;
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unsigned RegType = (EncodedReg >> 3) & 0x7;
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unsigned RegOffset = EncodedReg >> 6;
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switch (RegSpace) {
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default:
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llvm_unreachable("Unknown register space!");
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case PTXRegisterSpace::Reg:
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switch (RegType) {
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default:
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llvm_unreachable("Unknown register type!");
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case PTXRegisterType::Pred:
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OS << "p";
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break;
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case PTXRegisterType::B16:
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OS << "rh";
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break;
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case PTXRegisterType::B32:
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OS << "r";
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break;
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case PTXRegisterType::B64:
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OS << "rd";
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break;
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case PTXRegisterType::F32:
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OS << "f";
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break;
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case PTXRegisterType::F64:
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OS << "fd";
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break;
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}
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break;
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case PTXRegisterSpace::Return:
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OS << "ret";
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break;
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case PTXRegisterSpace::Argument:
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OS << "arg";
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break;
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}
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OS << RegOffset;
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}
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} // namespace llvm
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#endif
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@ -51,23 +51,23 @@ using namespace llvm;
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static const char PARAM_PREFIX[] = "__param_";
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static const char RETURN_PREFIX[] = "__ret_";
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static const char *getRegisterTypeName(unsigned RegNo,
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const MachineRegisterInfo& MRI) {
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const TargetRegisterClass *TRC = MRI.getRegClass(RegNo);
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#define TEST_REGCLS(cls, clsstr) \
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if (PTX::cls ## RegisterClass == TRC) return # clsstr;
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TEST_REGCLS(RegPred, pred);
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TEST_REGCLS(RegI16, b16);
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TEST_REGCLS(RegI32, b32);
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TEST_REGCLS(RegI64, b64);
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TEST_REGCLS(RegF32, b32);
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TEST_REGCLS(RegF64, b64);
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#undef TEST_REGCLS
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llvm_unreachable("Not in any register class!");
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return NULL;
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static const char *getRegisterTypeName(unsigned RegType) {
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switch (RegType) {
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default:
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llvm_unreachable("Unknown register type");
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case PTXRegisterType::Pred:
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return ".pred";
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case PTXRegisterType::B16:
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return ".b16";
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case PTXRegisterType::B32:
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return ".b32";
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case PTXRegisterType::B64:
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return ".b64";
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case PTXRegisterType::F32:
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return ".f32";
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case PTXRegisterType::F64:
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return ".f64";
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}
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}
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static const char *getStateSpaceName(unsigned addressSpace) {
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@ -188,32 +188,32 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
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unsigned numRegs;
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// pred
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numRegs = MFI->getNumRegistersForClass(PTX::RegPredRegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::Pred, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .pred %p<" << numRegs << ">;\n";
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// i16
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numRegs = MFI->getNumRegistersForClass(PTX::RegI16RegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::B16, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .b16 %rh<" << numRegs << ">;\n";
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// i32
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numRegs = MFI->getNumRegistersForClass(PTX::RegI32RegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::B32, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .b32 %r<" << numRegs << ">;\n";
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// i64
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numRegs = MFI->getNumRegistersForClass(PTX::RegI64RegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::B64, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .b64 %rd<" << numRegs << ">;\n";
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// f32
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numRegs = MFI->getNumRegistersForClass(PTX::RegF32RegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::F32, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .f32 %f<" << numRegs << ">;\n";
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// f64
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numRegs = MFI->getNumRegistersForClass(PTX::RegF64RegisterClass);
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numRegs = MFI->countRegisters(PTXRegisterType::F64, PTXRegisterSpace::Reg);
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if(numRegs > 0)
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os << "\t.reg .f64 %fd<" << numRegs << ">;\n";
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@ -368,7 +368,6 @@ void PTXAsmPrinter::EmitFunctionEntryLabel() {
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const PTXParamManager &PM = MFI->getParamManager();
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const bool isKernel = MFI->isKernel();
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const PTXSubtarget& ST = TM.getSubtarget<PTXSubtarget>();
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const MachineRegisterInfo& MRI = MF->getRegInfo();
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SmallString<128> decl;
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raw_svector_ostream os(decl);
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@ -391,7 +390,7 @@ void PTXAsmPrinter::EmitFunctionEntryLabel() {
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if (i != b)
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os << ", ";
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os << ".reg ." << getRegisterTypeName(*i, MRI) << ' '
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os << ".reg " << getRegisterTypeName(MFI->getRegisterType(*i)) << ' '
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<< MFI->getRegisterName(*i);
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}
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}
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@ -450,7 +449,7 @@ void PTXAsmPrinter::EmitFunctionEntryLabel() {
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if (i != b)
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os << ", ";
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os << ".reg ." << getRegisterTypeName(*i, MRI) << ' '
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os << ".reg " << getRegisterTypeName(MFI->getRegisterType(*i)) << ' '
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<< MFI->getRegisterName(*i);
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}
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}
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@ -521,34 +520,14 @@ MCOperand PTXAsmPrinter::GetSymbolRef(const MachineOperand &MO,
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MCOperand PTXAsmPrinter::lowerOperand(const MachineOperand &MO) {
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MCOperand MCOp;
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const PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
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const MachineRegisterInfo& MRI = MF->getRegInfo();
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const TargetRegisterClass* TRC;
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unsigned RegType;
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unsigned RegOffset;
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unsigned EncodedReg;
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switch (MO.getType()) {
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default:
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llvm_unreachable("Unknown operand type");
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case MachineOperand::MO_Register:
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if (MO.getReg() > 0) {
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TRC = MRI.getRegClass(MO.getReg());
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// Determine which PTX register type to use
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if (TRC == PTX::RegPredRegisterClass)
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RegType = PTXRegisterType::Pred;
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else if (TRC == PTX::RegI16RegisterClass)
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RegType = PTXRegisterType::B16;
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else if (TRC == PTX::RegI32RegisterClass)
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RegType = PTXRegisterType::B32;
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else if (TRC == PTX::RegI64RegisterClass)
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RegType = PTXRegisterType::B64;
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else if (TRC == PTX::RegF32RegisterClass)
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RegType = PTXRegisterType::F32;
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else if (TRC == PTX::RegF64RegisterClass)
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RegType = PTXRegisterType::F64;
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// Determine our virtual register offset
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RegOffset = MFI->getOffsetForRegister(TRC, MO.getReg());
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// Encode the register
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EncodedReg = (RegOffset << 4) | RegType;
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EncodedReg = MFI->getEncodedRegister(MO.getReg());
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} else {
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EncodedReg = 0;
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}
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@ -243,6 +243,30 @@ SDValue PTXTargetLowering::
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for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
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EVT RegVT = Ins[i].VT;
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TargetRegisterClass* TRC = getRegClassFor(RegVT);
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unsigned RegType;
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// Determine which register class we need
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if (RegVT == MVT::i1) {
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RegType = PTXRegisterType::Pred;
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}
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else if (RegVT == MVT::i16) {
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RegType = PTXRegisterType::B16;
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}
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else if (RegVT == MVT::i32) {
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RegType = PTXRegisterType::B32;
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}
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else if (RegVT == MVT::i64) {
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RegType = PTXRegisterType::B64;
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}
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else if (RegVT == MVT::f32) {
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RegType = PTXRegisterType::F32;
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}
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else if (RegVT == MVT::f64) {
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RegType = PTXRegisterType::F64;
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}
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else {
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llvm_unreachable("Unknown parameter type");
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}
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// Use a unique index in the instruction to prevent instruction folding.
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// Yes, this is a hack.
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@ -253,7 +277,7 @@ SDValue PTXTargetLowering::
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InVals.push_back(ArgValue);
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MFI->addArgReg(Reg);
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MFI->addRegister(Reg, RegType, PTXRegisterSpace::Argument);
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}
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}
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@ -304,25 +328,32 @@ SDValue PTXTargetLowering::
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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EVT RegVT = Outs[i].VT;
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TargetRegisterClass* TRC = 0;
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unsigned RegType;
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// Determine which register class we need
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if (RegVT == MVT::i1) {
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TRC = PTX::RegPredRegisterClass;
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RegType = PTXRegisterType::Pred;
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}
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else if (RegVT == MVT::i16) {
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TRC = PTX::RegI16RegisterClass;
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RegType = PTXRegisterType::B16;
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}
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else if (RegVT == MVT::i32) {
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TRC = PTX::RegI32RegisterClass;
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RegType = PTXRegisterType::B32;
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}
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else if (RegVT == MVT::i64) {
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TRC = PTX::RegI64RegisterClass;
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RegType = PTXRegisterType::B64;
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}
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else if (RegVT == MVT::f32) {
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TRC = PTX::RegF32RegisterClass;
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RegType = PTXRegisterType::F32;
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}
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else if (RegVT == MVT::f64) {
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TRC = PTX::RegF64RegisterClass;
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RegType = PTXRegisterType::F64;
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}
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else {
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llvm_unreachable("Unknown parameter type");
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@ -335,7 +366,7 @@ SDValue PTXTargetLowering::
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Chain = DAG.getNode(PTXISD::WRITE_PARAM, dl, MVT::Other, Copy, OutReg);
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MFI->addRetReg(Reg);
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MFI->addRegister(Reg, RegType, PTXRegisterSpace::Return);
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}
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}
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@ -825,17 +825,17 @@ let hasSideEffects = 1 in {
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///===- Parameter Passing Pseudo-Instructions -----------------------------===//
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def READPARAMPRED : InstPTX<(outs RegPred:$a), (ins i32imm:$b),
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"mov.pred\t$a, %param$b", []>;
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"mov.pred\t$a, %arg$b", []>;
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def READPARAMI16 : InstPTX<(outs RegI16:$a), (ins i32imm:$b),
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"mov.b16\t$a, %param$b", []>;
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"mov.b16\t$a, %arg$b", []>;
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def READPARAMI32 : InstPTX<(outs RegI32:$a), (ins i32imm:$b),
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"mov.b32\t$a, %param$b", []>;
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"mov.b32\t$a, %arg$b", []>;
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def READPARAMI64 : InstPTX<(outs RegI64:$a), (ins i32imm:$b),
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"mov.b64\t$a, %param$b", []>;
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"mov.b64\t$a, %arg$b", []>;
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def READPARAMF32 : InstPTX<(outs RegF32:$a), (ins i32imm:$b),
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"mov.f32\t$a, %param$b", []>;
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"mov.f32\t$a, %arg$b", []>;
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def READPARAMF64 : InstPTX<(outs RegF64:$a), (ins i32imm:$b),
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"mov.f64\t$a, %param$b", []>;
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"mov.f64\t$a, %arg$b", []>;
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def WRITEPARAMPRED : InstPTX<(outs), (ins RegPred:$a), "//w", []>;
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def WRITEPARAMI16 : InstPTX<(outs), (ins RegI16:$a), "//w", []>;
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@ -58,7 +58,20 @@ bool PTXMFInfoExtract::runOnMachineFunction(MachineFunction &MF) {
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for (unsigned i = 0; i < MRI.getNumVirtRegs(); ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
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MFI->addVirtualRegister(TRC, Reg);
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unsigned RegType;
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if (TRC == PTX::RegPredRegisterClass)
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RegType = PTXRegisterType::Pred;
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else if (TRC == PTX::RegI16RegisterClass)
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RegType = PTXRegisterType::B16;
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else if (TRC == PTX::RegI32RegisterClass)
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RegType = PTXRegisterType::B32;
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else if (TRC == PTX::RegI64RegisterClass)
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RegType = PTXRegisterType::B64;
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else if (TRC == PTX::RegF32RegisterClass)
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RegType = PTXRegisterType::F32;
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else if (TRC == PTX::RegF64RegisterClass)
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RegType = PTXRegisterType::F64;
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MFI->addRegister(Reg, RegType, PTXRegisterSpace::Reg);
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}
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return false;
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@ -35,15 +35,22 @@ private:
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DenseSet<unsigned> RegArgs;
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DenseSet<unsigned> RegRets;
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typedef std::vector<unsigned> RegisterList;
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typedef DenseMap<const TargetRegisterClass*, RegisterList> RegisterMap;
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typedef DenseMap<unsigned, std::string> RegisterNameMap;
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typedef DenseMap<int, std::string> FrameMap;
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RegisterMap UsedRegs;
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RegisterNameMap RegNames;
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FrameMap FrameSymbols;
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struct RegisterInfo {
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unsigned Reg;
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unsigned Type;
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unsigned Space;
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unsigned Offset;
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unsigned Encoded;
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};
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typedef DenseMap<unsigned, RegisterInfo> RegisterInfoMap;
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RegisterInfoMap RegInfo;
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PTXParamManager ParamManager;
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public:
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@ -51,13 +58,7 @@ public:
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PTXMachineFunctionInfo(MachineFunction &MF)
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: IsKernel(false) {
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UsedRegs[PTX::RegPredRegisterClass] = RegisterList();
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UsedRegs[PTX::RegI16RegisterClass] = RegisterList();
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UsedRegs[PTX::RegI32RegisterClass] = RegisterList();
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UsedRegs[PTX::RegI64RegisterClass] = RegisterList();
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UsedRegs[PTX::RegF32RegisterClass] = RegisterList();
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UsedRegs[PTX::RegF64RegisterClass] = RegisterList();
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}
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}
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/// getParamManager - Returns the PTXParamManager instance for this function.
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PTXParamManager& getParamManager() { return ParamManager; }
|
||||
@ -78,81 +79,106 @@ public:
|
||||
reg_iterator retreg_begin() const { return RegRets.begin(); }
|
||||
reg_iterator retreg_end() const { return RegRets.end(); }
|
||||
|
||||
/// addRegister - Adds a virtual register to the set of all used registers
|
||||
void addRegister(unsigned Reg, unsigned RegType, unsigned RegSpace) {
|
||||
if (!RegInfo.count(Reg)) {
|
||||
RegisterInfo Info;
|
||||
Info.Reg = Reg;
|
||||
Info.Type = RegType;
|
||||
Info.Space = RegSpace;
|
||||
|
||||
// Determine register offset
|
||||
Info.Offset = 0;
|
||||
for(RegisterInfoMap::const_iterator i = RegInfo.begin(),
|
||||
e = RegInfo.end(); i != e; ++i) {
|
||||
const RegisterInfo& RI = i->second;
|
||||
if (RI.Space == RegSpace)
|
||||
if (RI.Space != PTXRegisterSpace::Reg || RI.Type == Info.Type)
|
||||
Info.Offset++;
|
||||
}
|
||||
|
||||
// Encode the register data into a single register number
|
||||
Info.Encoded = (Info.Offset << 6) | (Info.Type << 3) | Info.Space;
|
||||
|
||||
RegInfo[Reg] = Info;
|
||||
|
||||
if (RegSpace == PTXRegisterSpace::Argument)
|
||||
RegArgs.insert(Reg);
|
||||
else if (RegSpace == PTXRegisterSpace::Return)
|
||||
RegRets.insert(Reg);
|
||||
}
|
||||
}
|
||||
|
||||
/// countRegisters - Returns the number of registers of the given type and
|
||||
/// space.
|
||||
unsigned countRegisters(unsigned RegType, unsigned RegSpace) const {
|
||||
unsigned Count = 0;
|
||||
for(RegisterInfoMap::const_iterator i = RegInfo.begin(), e = RegInfo.end();
|
||||
i != e; ++i) {
|
||||
const RegisterInfo& RI = i->second;
|
||||
if (RI.Type == RegType && RI.Space == RegSpace)
|
||||
Count++;
|
||||
}
|
||||
return Count;
|
||||
}
|
||||
|
||||
/// getEncodedRegister - Returns the encoded value of the register.
|
||||
unsigned getEncodedRegister(unsigned Reg) const {
|
||||
return RegInfo.lookup(Reg).Encoded;
|
||||
}
|
||||
|
||||
/// addRetReg - Adds a register to the set of return-value registers.
|
||||
void addRetReg(unsigned Reg) {
|
||||
if (!RegRets.count(Reg)) {
|
||||
RegRets.insert(Reg);
|
||||
std::string name;
|
||||
name = "%ret";
|
||||
name += utostr(RegRets.size() - 1);
|
||||
RegNames[Reg] = name;
|
||||
}
|
||||
}
|
||||
|
||||
/// addArgReg - Adds a register to the set of function argument registers.
|
||||
void addArgReg(unsigned Reg) {
|
||||
RegArgs.insert(Reg);
|
||||
std::string name;
|
||||
name = "%param";
|
||||
name += utostr(RegArgs.size() - 1);
|
||||
RegNames[Reg] = name;
|
||||
}
|
||||
|
||||
/// addVirtualRegister - Adds a virtual register to the set of all used
|
||||
/// registers in the function.
|
||||
void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) {
|
||||
std::string name;
|
||||
|
||||
// Do not count registers that are argument/return registers.
|
||||
if (!RegRets.count(Reg) && !RegArgs.count(Reg)) {
|
||||
UsedRegs[TRC].push_back(Reg);
|
||||
if (TRC == PTX::RegPredRegisterClass)
|
||||
name = "%p";
|
||||
else if (TRC == PTX::RegI16RegisterClass)
|
||||
name = "%rh";
|
||||
else if (TRC == PTX::RegI32RegisterClass)
|
||||
name = "%r";
|
||||
else if (TRC == PTX::RegI64RegisterClass)
|
||||
name = "%rd";
|
||||
else if (TRC == PTX::RegF32RegisterClass)
|
||||
name = "%f";
|
||||
else if (TRC == PTX::RegF64RegisterClass)
|
||||
name = "%fd";
|
||||
else
|
||||
llvm_unreachable("Invalid register class");
|
||||
|
||||
name += utostr(UsedRegs[TRC].size() - 1);
|
||||
RegNames[Reg] = name;
|
||||
}
|
||||
}
|
||||
|
||||
/// getRegisterName - Returns the name of the specified virtual register. This
|
||||
/// name is used during PTX emission.
|
||||
const char *getRegisterName(unsigned Reg) const {
|
||||
if (RegNames.count(Reg))
|
||||
return RegNames.find(Reg)->second.c_str();
|
||||
std::string getRegisterName(unsigned Reg) const {
|
||||
if (RegInfo.count(Reg)) {
|
||||
const RegisterInfo& RI = RegInfo.lookup(Reg);
|
||||
std::string Name;
|
||||
raw_string_ostream NameStr(Name);
|
||||
decodeRegisterName(NameStr, RI.Encoded);
|
||||
NameStr.flush();
|
||||
return Name;
|
||||
}
|
||||
else if (Reg == PTX::NoRegister)
|
||||
return "%noreg";
|
||||
else
|
||||
llvm_unreachable("Register not in register name map");
|
||||
}
|
||||
|
||||
/// getNumRegistersForClass - Returns the number of virtual registers that are
|
||||
/// used for the specified register class.
|
||||
unsigned getNumRegistersForClass(const TargetRegisterClass *TRC) const {
|
||||
return UsedRegs.lookup(TRC).size();
|
||||
/// getEncodedRegisterName - Returns the name of the encoded register.
|
||||
std::string getEncodedRegisterName(unsigned EncodedReg) const {
|
||||
std::string Name;
|
||||
raw_string_ostream NameStr(Name);
|
||||
decodeRegisterName(NameStr, EncodedReg);
|
||||
NameStr.flush();
|
||||
return Name;
|
||||
}
|
||||
|
||||
/// getRegisterType - Returns the type of the specified virtual register.
|
||||
unsigned getRegisterType(unsigned Reg) const {
|
||||
if (RegInfo.count(Reg))
|
||||
return RegInfo.lookup(Reg).Type;
|
||||
else
|
||||
llvm_unreachable("Unknown register");
|
||||
}
|
||||
|
||||
/// getOffsetForRegister - Returns the offset of the virtual register
|
||||
unsigned getOffsetForRegister(const TargetRegisterClass *TRC,
|
||||
unsigned Reg) const {
|
||||
const RegisterList &RegList = UsedRegs.lookup(TRC);
|
||||
for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
|
||||
if (RegList[i] == Reg)
|
||||
return i;
|
||||
}
|
||||
//llvm_unreachable("Unknown virtual register");
|
||||
return 0;
|
||||
unsigned getOffsetForRegister(unsigned Reg) const {
|
||||
if (RegInfo.count(Reg))
|
||||
return RegInfo.lookup(Reg).Offset;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/// getFrameSymbol - Returns the symbol name for the given FrameIndex.
|
||||
|
||||
@ -31,31 +31,31 @@ define ptx_device double @t1_f64() {
|
||||
}
|
||||
|
||||
define ptx_device i16 @t2_u16(i16 %x) {
|
||||
; CHECK: mov.b16 %ret{{[0-9]+}}, %param{{[0-9]+}};
|
||||
; CHECK: mov.b16 %ret{{[0-9]+}}, %arg{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
ret i16 %x
|
||||
}
|
||||
|
||||
define ptx_device i32 @t2_u32(i32 %x) {
|
||||
; CHECK: mov.b32 %ret{{[0-9]+}}, %param{{[0-9]+}};
|
||||
; CHECK: mov.b32 %ret{{[0-9]+}}, %arg{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
define ptx_device i64 @t2_u64(i64 %x) {
|
||||
; CHECK: mov.b64 %ret{{[0-9]+}}, %param{{[0-9]+}};
|
||||
; CHECK: mov.b64 %ret{{[0-9]+}}, %arg{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
ret i64 %x
|
||||
}
|
||||
|
||||
define ptx_device float @t3_f32(float %x) {
|
||||
; CHECK: mov.f32 %ret{{[0-9]+}}, %param{{[0-9]+}};
|
||||
; CHECK: mov.f32 %ret{{[0-9]+}}, %arg{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
ret float %x
|
||||
}
|
||||
|
||||
define ptx_device double @t3_f64(double %x) {
|
||||
; CHECK: mov.f64 %ret{{[0-9]+}}, %param{{[0-9]+}};
|
||||
; CHECK: mov.f64 %ret{{[0-9]+}}, %arg{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
ret double %x
|
||||
}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -march=ptx32 | FileCheck %s
|
||||
|
||||
; CHECK: .func (.reg .b32 %ret{{[0-9]+}}) test_parameter_order (.reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}}, .reg .b32 %param{{[0-9]+}})
|
||||
; CHECK: .func (.reg .b32 %ret{{[0-9]+}}) test_parameter_order (.reg .f32 %arg{{[0-9]+}}, .reg .b32 %arg{{[0-9]+}}, .reg .b32 %arg{{[0-9]+}}, .reg .f32 %arg{{[0-9]+}})
|
||||
define ptx_device i32 @test_parameter_order(float %a, i32 %b, i32 %c, float %d) {
|
||||
; CHECK: sub.u32 %ret{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
|
||||
%result = sub i32 %b, %c
|
||||
|
||||
Loading…
Reference in New Issue
Block a user