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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157867 91177308-0d34-0410-b5e6-96231b3b80d8
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7664f05326
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@ -43,19 +43,6 @@
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using namespace llvm;
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void MipsAsmPrinter::EmitInstrWithMacroNoAT(const MachineInstr *MI) {
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tat"));
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OutStreamer.EmitInstruction(TmpInst);
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if (MipsFI->getEmitNOAT())
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OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
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OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
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}
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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AsmPrinter::runOnMachineFunction(MF);
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@ -71,51 +58,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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unsigned Opc = MI->getOpcode();
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MCInst TmpInst0;
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SmallVector<MCInst, 4> MCInsts;
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switch (Opc) {
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case Mips::ULW:
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case Mips::ULH:
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case Mips::ULHu:
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case Mips::USW:
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case Mips::USH:
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case Mips::ULW_P8:
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case Mips::ULH_P8:
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case Mips::ULHu_P8:
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case Mips::USW_P8:
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case Mips::USH_P8:
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case Mips::ULD:
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case Mips::ULW64:
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case Mips::ULH64:
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case Mips::ULHu64:
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case Mips::USD:
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case Mips::USW64:
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case Mips::USH64:
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case Mips::ULD_P8:
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case Mips::ULW64_P8:
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case Mips::ULH64_P8:
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case Mips::ULHu64_P8:
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case Mips::USD_P8:
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case Mips::USW64_P8:
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case Mips::USH64_P8: {
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if (OutStreamer.hasRawTextSupport()) {
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EmitInstrWithMacroNoAT(MI);
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return;
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}
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MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
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!= MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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return;
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}
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default:
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break;
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}
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MCInstLowering.Lower(MI, TmpInst0);
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OutStreamer.EmitInstruction(TmpInst0);
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}
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@ -157,118 +157,6 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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}
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}
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void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst,
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4>& MCInsts) {
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unsigned Opc = MI->getOpcode();
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MCInst Instr1, Instr2, Instr3, Move;
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bool TwoInstructions = false;
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assert(MI->getNumOperands() == 3);
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assert(MI->getOperand(0).isReg());
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assert(MI->getOperand(1).isReg());
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MCOperand Target = LowerOperand(MI->getOperand(0));
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MCOperand Base = LowerOperand(MI->getOperand(1));
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MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
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MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
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MachineOperand UnLoweredName = MI->getOperand(2);
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MCOperand Name = LowerOperand(UnLoweredName);
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Move.setOpcode(Mips::ADDu);
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Move.addOperand(Target);
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Move.addOperand(ATReg);
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Move.addOperand(ZeroReg);
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switch (Opc) {
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case Mips::ULW: {
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// FIXME: only works for little endian right now
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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if (Base.getReg() == (Target.getReg())) {
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3 = Move;
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} else {
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TwoInstructions = true;
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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}
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break;
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}
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case Mips::ULHu: {
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// FIXME: only works for little endian right now
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::LBu);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LBu);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3.setOpcode(Mips::INS);
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Instr3.addOperand(Target);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(MCOperand::CreateImm(0x8));
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Instr3.addOperand(MCOperand::CreateImm(0x18));
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break;
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}
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case Mips::USW: {
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// FIXME: only works for little endian right now
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assert (Base.getReg() != Target.getReg());
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TwoInstructions = true;
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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Instr1.setOpcode(Mips::SWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::SWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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break;
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}
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case Mips::USH: {
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::SB);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(Name);
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Instr2.setOpcode(Mips::SRL);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Target);
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Instr2.addOperand(MCOperand::CreateImm(8));
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Instr3.setOpcode(Mips::SB);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(Base);
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Instr3.addOperand(AdjName);
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break;
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}
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default:
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// FIXME: need to add others
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llvm_unreachable("unaligned instruction not processed");
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}
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MCInsts.push_back(Instr1);
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MCInsts.push_back(Instr2);
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if (!TwoInstructions) MCInsts.push_back(Instr3);
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}
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// Create the following two instructions:
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// "lui $2, %hi(_gp_disp)"
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// "addiu $2, $2, %lo(_gp_disp)"
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@ -33,8 +33,6 @@ public:
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MipsMCInstLower(MipsAsmPrinter &asmprinter);
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void Initialize(Mangler *mang, MCContext* C);
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void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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void LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst, 4>& MCInsts);
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void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts);
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private:
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MCOperand LowerSymbolOperand(const MachineOperand &MO,
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