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Avoid depending on list orders and register numbering.

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This code is covered by test/CodeGen/ARM/arm-modifier.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157720 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-05-30 23:00:43 +00:00
parent 4aecc761c7
commit 4c91bdafac
1 changed files with 9 additions and 6 deletions
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13
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -441,16 +441,19 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
printOperand(MI, OpNum, O);
return false;
case 'y': // Print a VFP single precision register as indexed double.
// This uses the ordering of the alias table to get the first 'd' register
// that overlaps the 's' register. Also, s0 is an odd register, hence the
// odd modulus check below.
if (MI->getOperand(OpNum).isReg()) {
unsigned Reg = MI->getOperand(OpNum).getReg();
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
(((Reg % 2) == 1) ? "[0]" : "[1]");
// Find the 'd' register that has this 's' register as a sub-register,
// and determine the lane number.
for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
if (!ARM::DPRRegClass.contains(*SR))
continue;
bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
return false;
}
}
return true;
case 'B': // Bitwise inverse of integer or symbol without a preceding #.
if (!MI->getOperand(OpNum).isImm())