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ARM: Use ldrd/strd to spill 64-bit pairs when available.
This allows common sp-offsets to be part of the instruction and is probably faster on modern CPUs too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179977 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -747,10 +747,10 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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Mov->addRegisterKilled(SrcReg, TRI);
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}
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static const
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MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
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unsigned Reg, unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) {
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const MachineInstrBuilder &
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ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) const {
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if (!SubIdx)
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return MIB.addReg(Reg, State);
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@ -795,12 +795,22 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
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.addFrameIndex(FI))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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if (Subtarget.hasV5TEOps()) {
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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} else {
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// Fallback to STM instruction, which has existed since the dawn of
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// time.
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
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.addFrameIndex(FI).addMemOperand(MMO));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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}
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} else
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llvm_unreachable("Unknown reg class!");
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break;
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@ -948,7 +958,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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MachineMemOperand *MMO =
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@ -975,12 +984,24 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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unsigned LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA : ARM::LDMIA;
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, I, DL, get(LdmOpc))
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.addFrameIndex(FI).addMemOperand(MMO));
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MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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MachineInstrBuilder MIB;
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if (Subtarget.hasV5TEOps()) {
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MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
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AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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} else {
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// Fallback to LDM instruction, which has existed since the dawn of
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// time.
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MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
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.addFrameIndex(FI).addMemOperand(MMO));
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MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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}
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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} else
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@ -141,6 +141,10 @@ public:
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MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
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const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) const;
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virtual bool produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const;
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@ -19,6 +19,7 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/CommandLine.h"
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@ -126,25 +127,41 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
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RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
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RC == &ARM::GPRnopcRegClass) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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return;
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}
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ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
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}
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@ -153,24 +170,42 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
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RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
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RC == &ARM::GPRnopcRegClass) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
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// Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
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AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
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MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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AddDefaultPred(MIB);
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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return;
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}
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ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
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}
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@ -514,6 +549,15 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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Offset = -Offset;
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isSub = true;
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}
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} else if (AddrMode == ARMII::AddrModeT2_i8s4) {
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Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
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NumBits = 8;
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// MCInst operand has already scaled value.
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Scale = 1;
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if (Offset < 0) {
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isSub = true;
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Offset = -Offset;
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}
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} else {
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llvm_unreachable("Unsupported addressing mode!");
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}
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@ -1,29 +1,43 @@
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; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
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; RUN: llc -mtriple=armv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s --check-prefix=INSTRS-ARE-THUMB
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define void @foo(i64* %addr) {
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%val1 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val2 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val3 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val4 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val5 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val6 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val7 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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; Key point is that enough 64-bit paired GPR values are live that
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; one of them has to be spilled. This used to cause an abort because
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; an LDMIA was created with both a FrameIndex and an offset, which
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; is not allowed.
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; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
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; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
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; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
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; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
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; We also want to ensure the register scavenger is working (i.e. an
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; offset from sp can be generated), so we need two spills.
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; CHECK: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
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; CHECK: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK-WITHOUT-LDRD: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
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; CHECK-WITHOUT-LDRD: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK-WITHOUT-LDRD: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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; In principle LLVM may have to recalculate the offset. At the moment
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; it reuses the original though.
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; CHECK: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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; Make sure we are actually creating the Thumb versions of the spill
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; instructions.
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; INSTRS-ARE-THUMB: t2STRDi8
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; INSTRS-ARE-THUMB: t2LDRDi8
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store volatile i64 %val1, i64* %addr
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store volatile i64 %val2, i64* %addr
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