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[Hexagon] Replacing old fadd/fsub instructions and updating references.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226176 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-15 16:30:07 +00:00
parent d048b3be70
commit 4ce3b1e4ce
4 changed files with 19 additions and 34 deletions
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14
lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1109,6 +1109,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
setOperationAction(ISD::FDIV, MVT::f64, Expand);
setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
setOperationAction(ISD::FSIN, MVT::f32, Expand);
@ -1117,7 +1120,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
if (Subtarget.hasV5TOps()) {
// Hexagon V5 Support.
setOperationAction(ISD::FADD, MVT::f32, Legal);
setOperationAction(ISD::FADD, MVT::f64, Legal);
setOperationAction(ISD::FADD, MVT::f64, Expand);
setOperationAction(ISD::FSUB, MVT::f32, Legal);
setOperationAction(ISD::FSUB, MVT::f64, Expand);
setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
@ -1202,11 +1207,14 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
setOperationAction(ISD::FADD, MVT::f64, Expand);
setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
setOperationAction(ISD::FADD, MVT::f32, Expand);
setOperationAction(ISD::FADD, MVT::f64, Expand);
setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
setOperationAction(ISD::FSUB, MVT::f32, Expand);
setOperationAction(ISD::FSUB, MVT::f64, Expand);
setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);

35
lib/Target/Hexagon/HexagonInstrInfoV5.td
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@ -148,6 +148,12 @@ let isCommutable = 1, isCodeGenOnly = 0 in {
let isCodeGenOnly = 0 in
def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
(F2_sfadd F32:$src1, F32:$src2)>;
def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
(F2_sfsub F32:$src1, F32:$src2)>;
let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
@ -489,35 +495,6 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
}
// Add
let isCommutable = 1 in
def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = sfadd($src1, $src2)",
[(set IntRegs:$dst, (fadd IntRegs:$src1, IntRegs:$src2))]>,
Requires<[HasV5T]>;
let isCommutable = 1 in
def fADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2),
"$dst = dfadd($src1, $src2)",
[(set DoubleRegs:$dst, (fadd DoubleRegs:$src1,
DoubleRegs:$src2))]>,
Requires<[HasV5T]>;
def fSUB_rr : ALU64_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = sfsub($src1, $src2)",
[(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
Requires<[HasV5T]>;
def fSUB64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
DoubleRegs:$src2),
"$dst = dfsub($src1, $src2)",
[(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
DoubleRegs:$src2))]>,
Requires<[HasV5T]>;
let isCommutable = 1 in
def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),

2
test/CodeGen/Hexagon/dadd.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate double precision floating point add in V5.
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfadd(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
; CHECK: call __hexagon_adddf3
define i32 @main() nounwind {

2
test/CodeGen/Hexagon/dsub.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate double precision floating point subtract in V5.
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfsub(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
; CHECK: call __hexagon_subdf3
define i32 @main() nounwind {
entry: