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ARM more NEON VLD/VST composite physical register refactoring.

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Register pair, all lanes subscripting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2012-03-06 23:10:38 +00:00
parent c511c2827d
commit 4d0983a4d7
6 changed files with 59 additions and 40 deletions
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lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+4 -5
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@@ -1104,11 +1104,10 @@ void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
}
void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,