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Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.

Browse Source 
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239467 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-06-10 12:11:26 +00:00
parent fff114c890
commit 4d13f315d1
64 changed files with 153 additions and 165 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
include/llvm/MC/MCSubtargetInfo.h
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@ -27,7 +27,7 @@ class StringRef;
/// MCSubtargetInfo - Generic base class for all target subtargets. /// MCSubtargetInfo - Generic base class for all target subtargets.
/// ///
class MCSubtargetInfo { class MCSubtargetInfo {
std::string TargetTriple; // Target triple Triple TargetTriple; // Target triple
std::string CPU; // CPU being targeted. std::string CPU; // CPU being targeted.
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
@ -45,20 +45,17 @@ class MCSubtargetInfo {
FeatureBitset FeatureBits; // Feature bits for current CPU + FS FeatureBitset FeatureBits; // Feature bits for current CPU + FS
public: public:
void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD, ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched, const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR, const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const MCReadAdvanceEntry *RA, const InstrStage *IS,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP); const unsigned *OC, const unsigned *FP);
/// getTargetTriple - Return the target triple string. /// getTargetTriple - Return the target triple string.
StringRef getTargetTriple() const { const Triple &getTargetTriple() const { return TargetTriple; }
return TargetTriple;
}
/// getCPU - Return the CPU string. /// getCPU - Return the CPU string.
StringRef getCPU() const { StringRef getCPU() const {

10
include/llvm/Support/TargetRegistry.h
View File

@ -98,7 +98,7 @@ public:
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info); typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
StringRef CPU, StringRef CPU,
StringRef Features); StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)( typedef TargetMachine *(*TargetMachineCtorTy)(
@ -334,18 +334,18 @@ public:
/// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
/// ///
/// \param Triple This argument is used to determine the target machine /// \param TheTriple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the /// either the target triple from the module, or the target triple of the
/// host if that does not exist. /// host if that does not exist.
/// \param CPU This specifies the name of the target CPU. /// \param CPU This specifies the name of the target CPU.
/// \param Features This specifies the string representation of the /// \param Features This specifies the string representation of the
/// additional target features. /// additional target features.
MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
StringRef Features) const { StringRef Features) const {
if (!MCSubtargetInfoCtorFn) if (!MCSubtargetInfoCtorFn)
return nullptr; return nullptr;
return MCSubtargetInfoCtorFn(Triple, CPU, Features); return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
} }
/// createTargetMachine - Create a target specific machine implementation /// createTargetMachine - Create a target specific machine implementation
@ -1056,7 +1056,7 @@ template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
} }
private: private:
static MCSubtargetInfo *Allocator(StringRef /*TT*/, StringRef /*CPU*/, static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
StringRef /*FS*/) { StringRef /*FS*/) {
return new MCSubtargetInfoImpl(); return new MCSubtargetInfoImpl();
} }

17
lib/MC/MCSubtargetInfo.cpp
View File

@ -34,17 +34,12 @@ MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
CPUSchedModel = MCSchedModel::GetDefaultSchedModel(); CPUSchedModel = MCSchedModel::GetDefaultSchedModel();
} }
void void MCSubtargetInfo::InitMCSubtargetInfo(
MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, const Triple &TT, StringRef C, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
const SubtargetInfoKV *ProcSched, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const MCWriteProcResEntry *WPR, const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP) {
TargetTriple = TT; TargetTriple = TT;
CPU = C; CPU = C;
ProcFeatures = PF; ProcFeatures = PF;

8
lib/Target/AArch64/AArch64Subtarget.cpp
View File

@ -42,14 +42,12 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
return *this; return *this;
} }
AArch64Subtarget::AArch64Subtarget(const std::string &TT, AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &CPU,
const std::string &FS, const std::string &FS,
const TargetMachine &TM, bool LittleEndian) const TargetMachine &TM, bool LittleEndian)
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
HasV8_1aOps(false), HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(), IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)), InstrInfo(initializeSubtargetDependencies(FS)),
TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {} TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}

3
lib/Target/AArch64/AArch64Subtarget.h
View File

@ -29,6 +29,7 @@
namespace llvm { namespace llvm {
class GlobalValue; class GlobalValue;
class StringRef; class StringRef;
class Triple;
class AArch64Subtarget : public AArch64GenSubtargetInfo { class AArch64Subtarget : public AArch64GenSubtargetInfo {
protected: protected:
@ -71,7 +72,7 @@ private:
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
AArch64Subtarget(const std::string &TT, const std::string &CPU, AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM, const std::string &FS, const TargetMachine &TM,
bool LittleEndian); bool LittleEndian);

3
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -156,7 +156,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle); I = llvm::make_unique<AArch64Subtarget>(Triple(TargetTriple), CPU, FS,
*this, isLittle);
} }
return I.get(); return I.get();
} }

2
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View File

@ -41,7 +41,7 @@ static MCInstrInfo *createAArch64MCInstrInfo() {
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
if (CPU.empty()) if (CPU.empty())

2
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -564,7 +564,7 @@ void ARMAsmPrinter::emitAttributes() {
// anyhow. // anyhow.
// FIXME: For ifunc related functions we could iterate over and look // FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one. // for a feature string that doesn't match the default one.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = TM.getTargetCPU(); StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);

5
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -106,7 +106,7 @@ ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
return new ARMFrameLowering(STI); return new ARMFrameLowering(STI);
} }
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
const ARMBaseTargetMachine &TM, bool IsLittle) const ARMBaseTargetMachine &TM, bool IsLittle)
: ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
@ -187,8 +187,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
// Insert the architecture feature derived from the target triple into the // Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied // feature string. This is important for setting features that are implied
// based on the architecture version. // based on the architecture version.
std::string ArchFS = std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();

4
lib/Target/ARM/ARMSubtarget.h
View File

@ -237,8 +237,8 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); const ARMBaseTargetMachine &TM, bool IsLittle);
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call. /// that still makes it profitable to inline the call.

5
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -180,7 +180,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
CPU, FS, Options, RM, CM, OL), CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)), TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) {
// Default to triple-appropriate float ABI // Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default) if (Options.FloatABIType == FloatABI::Default)
@ -221,7 +221,8 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle); I = llvm::make_unique<ARMSubtarget>(Triple(TargetTriple), CPU, FS, *this,
isLittle);
} }
return I.get(); return I.get();
} }

2
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
View File

@ -24,7 +24,7 @@ class ARMAsmBackend : public MCAsmBackend {
bool IsLittleEndian; // Big or little endian. bool IsLittleEndian; // Big or little endian.
public: public:
ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
: MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT.str(), "", "")), : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
isThumbMode(TT.getArchName().startswith("thumb")), isThumbMode(TT.getArchName().startswith("thumb")),
IsLittleEndian(IsLittle) {} IsLittleEndian(IsLittle) {}

17
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -130,16 +130,13 @@ static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "ARMGenSubtargetInfo.inc" #include "ARMGenSubtargetInfo.inc"
std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { bool isThumb =
Triple triple(TT); TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
bool isThumb = triple.getArch() == Triple::thumb ||
triple.getArch() == Triple::thumbeb;
bool NoCPU = CPU == "generic" || CPU.empty(); bool NoCPU = CPU == "generic" || CPU.empty();
std::string ARMArchFeature; std::string ARMArchFeature;
switch (triple.getSubArch()) { switch (TT.getSubArch()) {
default: default:
llvm_unreachable("invalid sub-architecture for ARM"); llvm_unreachable("invalid sub-architecture for ARM");
case Triple::ARMSubArch_v8: case Triple::ARMSubArch_v8:
@ -240,7 +237,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
ARMArchFeature += ",+thumb-mode"; ARMArchFeature += ",+thumb-mode";
} }
if (triple.isOSNaCl()) { if (TT.isOSNaCl()) {
if (ARMArchFeature.empty()) if (ARMArchFeature.empty())
ARMArchFeature = "+nacl-trap"; ARMArchFeature = "+nacl-trap";
else else
@ -250,8 +247,8 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
return ARMArchFeature; return ARMArchFeature;
} }
MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())

10
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -40,12 +40,12 @@ extern Target TheARMLETarget, TheThumbLETarget;
extern Target TheARMBETarget, TheThumbBETarget; extern Target TheARMBETarget, TheThumbBETarget;
namespace ARM_MC { namespace ARM_MC {
std::string ParseARMTriple(StringRef TT, StringRef CPU); std::string ParseARMTriple(const Triple &TT, StringRef CPU);
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry. /// do not need to go through TargetRegistry.
MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
} }
MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);

2
lib/Target/BPF/BPFSubtarget.cpp
View File

@ -25,7 +25,7 @@ using namespace llvm;
void BPFSubtarget::anchor() {} void BPFSubtarget::anchor() {}
BPFSubtarget::BPFSubtarget(const std::string &TT, const std::string &CPU, BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}

4
lib/Target/BPF/BPFSubtarget.h
View File

@ -38,8 +38,8 @@ class BPFSubtarget : public BPFGenSubtargetInfo {
public: public:
// This constructor initializes the data members to match that // This constructor initializes the data members to match that
// of the specified triple. // of the specified triple.
BPFSubtarget(const std::string &TT, const std::string &CPU, BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const TargetMachine &TM); const TargetMachine &TM);
// ParseSubtargetFeatures - Parses features string setting specified // ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen. // subtarget options. Definition of function is auto generated by tblgen.

2
lib/Target/BPF/BPFTargetMachine.cpp
View File

@ -43,7 +43,7 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU,
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
namespace { namespace {

4
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
View File

@ -46,8 +46,8 @@ static MCRegisterInfo *createBPFMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createBPFMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitBPFMCSubtargetInfo(X, TT, CPU, FS); InitBPFMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

4
lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -70,8 +70,8 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
return *this; return *this;
} }
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
const TargetMachine &TM) StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()), FrameLowering() { TSInfo(*TM.getDataLayout()), FrameLowering() {

2
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -52,7 +52,7 @@ private:
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
public: public:
HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM); const TargetMachine &TM);
/// getInstrItins - Return the instruction itineraries based on subtarget /// getInstrItins - Return the instruction itineraries based on subtarget

2
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -76,7 +76,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()), TLOF(make_unique<HexagonTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
View File

@ -48,7 +48,7 @@ static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitHexagonMCSubtargetInfo(X, TT, CPU, FS); InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

4
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -43,8 +43,8 @@ static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitMSP430MCSubtargetInfo(X, TT, CPU, FS); InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

2
lib/Target/MSP430/MSP430Subtarget.cpp
View File

@ -31,7 +31,7 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
return *this; return *this;
} }
MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &CPU, MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),

2
lib/Target/MSP430/MSP430Subtarget.h
View File

@ -41,7 +41,7 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
MSP430Subtarget(const std::string &TT, const std::string &CPU, MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);

2
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
// FIXME: Check DataLayout string. // FIXME: Check DataLayout string.
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

10
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -43,11 +43,9 @@ using namespace llvm;
/// Select the Mips CPU for the given triple and cpu name. /// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsSubtarget.cpp /// FIXME: Merge with the copy in MipsSubtarget.cpp
StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) { StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
if (CPU.empty() || CPU == "generic") { if (CPU.empty() || CPU == "generic") {
Triple TheTriple(TT); if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel)
CPU = "mips32"; CPU = "mips32";
else else
CPU = "mips64"; CPU = "mips64";
@ -67,8 +65,8 @@ static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU); CPU = MIPS_MC::selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS); InitMipsMCSubtargetInfo(X, TT, CPU, FS);

2
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -59,7 +59,7 @@ MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit); bool IsLittleEndian, bool Is64Bit);
namespace MIPS_MC { namespace MIPS_MC {
StringRef selectMipsCPU(StringRef TT, StringRef CPU); StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
} }
} // End llvm namespace } // End llvm namespace

5
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -694,9 +694,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// clean anyhow. // clean anyhow.
// FIXME: For ifunc related functions we could iterate over and look // FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one. // for a feature string that doesn't match the default one.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
MIPS_MC::selectMipsCPU(TM.getTargetTriple(), TM.getTargetCPU());
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM); const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);

5
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -59,7 +59,7 @@ static cl::opt<bool>
void MipsSubtarget::anchor() { } void MipsSubtarget::anchor() { }
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, bool little, const std::string &FS, bool little,
const MipsTargetMachine &TM) const MipsTargetMachine &TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
@ -141,7 +141,8 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
MipsSubtarget & MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) { const TargetMachine &TM) {
std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); std::string CPUName =
MIPS_MC::selectMipsCPU(Triple(TM.getTargetTriple()), CPU);
// Parse features string. // Parse features string.
ParseSubtargetFeatures(CPUName, FS); ParseSubtargetFeatures(CPUName, FS);

5
lib/Target/Mips/MipsSubtarget.h
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@ -161,9 +161,8 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, bool little, bool little, const MipsTargetMachine &TM);
const MipsTargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.

14
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -92,11 +92,14 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
CPU, FS, Options, RM, CM, OL), CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), Subtarget(nullptr),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", DefaultSubtarget(Triple(TT), CPU, FS, isLittle, *this),
NoMips16Subtarget(Triple(TT), CPU,
FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, *this), isLittle, *this),
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", Mips16Subtarget(Triple(TT), CPU,
isLittle, *this) { FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle,
*this) {
Subtarget = &DefaultSubtarget; Subtarget = &DefaultSubtarget;
initAsmInfo(); initAsmInfo();
} }
@ -157,7 +160,8 @@ MipsTargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this); I = llvm::make_unique<MipsSubtarget>(Triple(TargetTriple), CPU, FS,
isLittle, *this);
} }
return I.get(); return I.get();
} }

2
lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
View File

@ -45,7 +45,7 @@ static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitNVPTXMCSubtargetInfo(X, TT, CPU, FS); InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

2
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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@ -808,7 +808,7 @@ bool NVPTXAsmPrinter::doInitialization(Module &M) {
// Construct a default subtarget off of the TargetMachine defaults. The // Construct a default subtarget off of the TargetMachine defaults. The
// rest of NVPTX isn't friendly to change subtargets per function and // rest of NVPTX isn't friendly to change subtargets per function and
// so the default TargetMachine will have all of the options. // so the default TargetMachine will have all of the options.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = TM.getTargetCPU(); StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM); const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM);

2
lib/Target/NVPTX/NVPTXSubtarget.cpp
View File

@ -43,7 +43,7 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
return *this; return *this;
} }
NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
const NVPTXTargetMachine &TM) const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),

2
lib/Target/NVPTX/NVPTXSubtarget.h
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@ -52,7 +52,7 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified module. /// of the specified module.
/// ///
NVPTXSubtarget(const std::string &TT, const std::string &CPU, NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const NVPTXTargetMachine &TM); const std::string &FS, const NVPTXTargetMachine &TM);
const TargetFrameLowering *getFrameLowering() const override { const TargetFrameLowering *getFrameLowering() const override {

2
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -91,7 +91,7 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
CM, OL), CM, OL),
is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()), is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
if (Triple(TT).getOS() == Triple::NVCL) if (Triple(TT).getOS() == Triple::NVCL)
drvInterface = NVPTX::NVCL; drvInterface = NVPTX::NVCL;
else else

4
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -63,8 +63,8 @@ static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitPPCMCSubtargetInfo(X, TT, CPU, FS); InitPPCMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

2
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -47,7 +47,7 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
return *this; return *this;
} }
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const PPCTargetMachine &TM) const std::string &FS, const PPCTargetMachine &TM)
: PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
IsPPC64(TargetTriple.getArch() == Triple::ppc64 || IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||

4
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -135,8 +135,8 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
PPCSubtarget(const std::string &TT, const std::string &CPU, PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const PPCTargetMachine &TM); const PPCTargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.

2
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -217,7 +217,7 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<PPCSubtarget>( I = llvm::make_unique<PPCSubtarget>(
TargetTriple, CPU, Triple(TargetTriple), CPU,
// FIXME: It would be good to have the subtarget additions here // FIXME: It would be good to have the subtarget additions here
// not necessary. Anything that turns them on/off (overrides) ends // not necessary. Anything that turns them on/off (overrides) ends
// up being put at the end of the feature string, but the defaults // up being put at the end of the feature string, but the defaults

13
lib/Target/R600/AMDGPUSubtarget.cpp
View File

@ -32,8 +32,8 @@ using namespace llvm;
#include "AMDGPUGenSubtargetInfo.inc" #include "AMDGPUGenSubtargetInfo.inc"
AMDGPUSubtarget & AMDGPUSubtarget &
AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU, AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef FS) { StringRef GPU, StringRef FS) {
// Determine default and user-specified characteristics // Determine default and user-specified characteristics
// On SI+, we want FP64 denormals to be on by default. FP32 denormals can be // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
// enabled, but some instructions do not respect them and they run at the // enabled, but some instructions do not respect them and they run at the
@ -46,7 +46,7 @@ AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU,
SmallString<256> FullFS("+promote-alloca,+fp64-denormals,"); SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
FullFS += FS; FullFS += FS;
if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn) if (GPU == "" && TT.getArch() == Triple::amdgcn)
GPU = "SI"; GPU = "SI";
ParseSubtargetFeatures(GPU, FullFS); ParseSubtargetFeatures(GPU, FullFS);
@ -61,7 +61,7 @@ AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU,
return *this; return *this;
} }
AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
TargetMachine &TM) TargetMachine &TM)
: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
DumpCode(false), R600ALUInst(false), HasVertexCache(false), DumpCode(false), R600ALUInst(false), HasVertexCache(false),
@ -70,9 +70,8 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true), CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false), EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
EnableVGPRSpilling(false), SGPRInitBug(false), EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
LDSBankCount(0),
FrameLowering(TargetFrameLowering::StackGrowsUp, FrameLowering(TargetFrameLowering::StackGrowsUp,
64 * 16, // Maximum stack alignment (long16) 64 * 16, // Maximum stack alignment (long16)
0), 0),

7
lib/Target/R600/AMDGPUSubtarget.h
View File

@ -85,9 +85,10 @@ private:
Triple TargetTriple; Triple TargetTriple;
public: public:
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM); AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU, TargetMachine &TM);
StringRef FS); AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
StringRef GPU, StringRef FS);
const AMDGPUFrameLowering *getFrameLowering() const override { const AMDGPUFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;

4
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -73,8 +73,8 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
OptLevel), OptLevel),
TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this), TLOF(new TargetLoweringObjectFileELF()),
IntrinsicInfo() { Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() {
setRequiresStructuredCFG(true); setRequiresStructuredCFG(true);
initAsmInfo(); initAsmInfo();
} }

4
lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
View File

@ -49,8 +49,8 @@ static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo * X = new MCSubtargetInfo(); MCSubtargetInfo * X = new MCSubtargetInfo();
InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

4
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@ -76,7 +76,9 @@ class SparcAsmParser : public MCTargetAsmParser {
bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
bool parseDirectiveWord(unsigned Size, SMLoc L); bool parseDirectiveWord(unsigned Size, SMLoc L);
bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } bool is64Bit() const {
return STI.getTargetTriple().getArchName().startswith("sparcv9");
}
void expandSET(MCInst &Inst, SMLoc IDLoc, void expandSET(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);

7
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -63,12 +63,11 @@ static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
Triple TheTriple(TT);
if (CPU.empty()) if (CPU.empty())
CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
InitSparcMCSubtargetInfo(X, TT, CPU, FS); InitSparcMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }

2
lib/Target/Sparc/SparcSubtarget.cpp
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@ -49,7 +49,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
return *this; return *this;
} }
SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, TargetMachine &TM, const std::string &FS, TargetMachine &TM,
bool is64Bit) bool is64Bit)
: SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),

2
lib/Target/Sparc/SparcSubtarget.h
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@ -43,7 +43,7 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
SparcFrameLowering FrameLowering; SparcFrameLowering FrameLowering;
public: public:
SparcSubtarget(const std::string &TT, const std::string &CPU, SparcSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, TargetMachine &TM, bool is64bit); const std::string &FS, TargetMachine &TM, bool is64bit);
const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }

2
lib/Target/Sparc/SparcTargetMachine.cpp
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@ -62,7 +62,7 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()), TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) { Subtarget(Triple(TT), CPU, FS, *this, is64bit) {
initAsmInfo(); initAsmInfo();
} }

5
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
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@ -154,9 +154,8 @@ static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, static MCSubtargetInfo *
StringRef CPU, createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitSystemZMCSubtargetInfo(X, TT, CPU, FS); InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

9
lib/Target/SystemZ/SystemZSubtarget.cpp
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@ -32,8 +32,7 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
return *this; return *this;
} }
SystemZSubtarget::SystemZSubtarget(const std::string &TT, SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
const std::string &CPU,
const std::string &FS, const std::string &FS,
const TargetMachine &TM) const TargetMachine &TM)
: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
@ -41,9 +40,9 @@ SystemZSubtarget::SystemZSubtarget(const std::string &TT,
HasPopulationCount(false), HasFastSerialization(false), HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasTransactionalExecution(false), HasProcessorAssist(false), HasTransactionalExecution(false), HasProcessorAssist(false),
HasVector(false), HasVector(false), TargetTriple(TT),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} TSInfo(*TM.getDataLayout()), FrameLowering() {}
// Return true if GV binds locally under reloc model RM. // Return true if GV binds locally under reloc model RM.
static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) { static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) {

2
lib/Target/SystemZ/SystemZSubtarget.h
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@ -56,7 +56,7 @@ private:
SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU, SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
StringRef FS); StringRef FS);
public: public:
SystemZSubtarget(const std::string &TT, const std::string &CPU, SystemZSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
const TargetFrameLowering *getFrameLowering() const override { const TargetFrameLowering *getFrameLowering() const override {

6
lib/Target/SystemZ/SystemZTargetMachine.cpp
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@ -84,10 +84,10 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
TT, CPU, FS, Options, RM, CM, OL), RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

11
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -42,12 +42,11 @@ using namespace llvm;
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "X86GenSubtargetInfo.inc" #include "X86GenSubtargetInfo.inc"
std::string X86_MC::ParseX86Triple(StringRef TT) { std::string X86_MC::ParseX86Triple(const Triple &TT) {
Triple TheTriple(TT);
std::string FS; std::string FS;
if (TheTriple.getArch() == Triple::x86_64) if (TT.getArch() == Triple::x86_64)
FS = "+64bit-mode,-32bit-mode,-16bit-mode"; FS = "+64bit-mode,-32bit-mode,-16bit-mode";
else if (TheTriple.getEnvironment() != Triple::CODE16) else if (TT.getEnvironment() != Triple::CODE16)
FS = "-64bit-mode,+32bit-mode,-16bit-mode"; FS = "-64bit-mode,+32bit-mode,-16bit-mode";
else else
FS = "-64bit-mode,-32bit-mode,+16bit-mode"; FS = "-64bit-mode,-32bit-mode,+16bit-mode";
@ -75,8 +74,8 @@ void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
} }
} }
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT); std::string ArchFS = X86_MC::ParseX86Triple(TT);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())

14
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
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@ -52,16 +52,16 @@ namespace N86 {
} }
namespace X86_MC { namespace X86_MC {
std::string ParseX86Triple(StringRef TT); std::string ParseX86Triple(const Triple &TT);
unsigned getDwarfRegFlavour(Triple TT, bool isEH); unsigned getDwarfRegFlavour(Triple TT, bool isEH);
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry. /// do not need to go through TargetRegistry.
MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
} }
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,

2
lib/Target/X86/X86Subtarget.cpp
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@ -287,7 +287,7 @@ X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
return *this; return *this;
} }
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const X86TargetMachine &TM, const std::string &FS, const X86TargetMachine &TM,
unsigned StackAlignOverride) unsigned StackAlignOverride)
: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others), : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),

5
lib/Target/X86/X86Subtarget.h
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@ -253,9 +253,8 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const X86TargetMachine &TM, const X86TargetMachine &TM, unsigned StackAlignOverride);
unsigned StackAlignOverride);
const X86TargetLowering *getTargetLowering() const override { const X86TargetLowering *getTargetLowering() const override {
return &TLInfo; return &TLInfo;

4
lib/Target/X86/X86TargetMachine.cpp
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@ -97,7 +97,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
: LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
RM, CM, OL), RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { Subtarget(Triple(TT), CPU, FS, *this, Options.StackAlignmentOverride) {
// Windows stack unwinder gets confused when execution flow "falls through" // Windows stack unwinder gets confused when execution flow "falls through"
// after a call to 'noreturn' function. // after a call to 'noreturn' function.
// To prevent that, we emit a trap for 'unreachable' IR instructions. // To prevent that, we emit a trap for 'unreachable' IR instructions.
@ -148,7 +148,7 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this, I = llvm::make_unique<X86Subtarget>(Triple(TargetTriple), CPU, FS, *this,
Options.StackAlignmentOverride); Options.StackAlignmentOverride);
} }
return I.get(); return I.get();

4
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
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@ -46,8 +46,8 @@ static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
return X; return X;
} }
static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitXCoreMCSubtargetInfo(X, TT, CPU, FS); InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

2
lib/Target/XCore/XCoreSubtarget.cpp
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@ -25,7 +25,7 @@ using namespace llvm;
void XCoreSubtarget::anchor() { } void XCoreSubtarget::anchor() { }
XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()) {} TLInfo(TM, *this), TSInfo(*TM.getDataLayout()) {}

2
lib/Target/XCore/XCoreSubtarget.h
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@ -40,7 +40,7 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
XCoreSubtarget(const std::string &TT, const std::string &CPU, XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified

2
lib/Target/XCore/XCoreTargetMachine.cpp
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@ -31,7 +31,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, RM, CM, OL), TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<XCoreTargetObjectFile>()), TLOF(make_unique<XCoreTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

9
utils/TableGen/SubtargetEmitter.cpp
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@ -1437,7 +1437,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
// MCInstrInfo initialization routine. // MCInstrInfo initialization routine.
OS << "static inline void Init" << Target OS << "static inline void Init" << Target
<< "MCSubtargetInfo(MCSubtargetInfo *II, " << "MCSubtargetInfo(MCSubtargetInfo *II, "
<< "StringRef TT, StringRef CPU, StringRef FS) {\n"; << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
if (NumFeatures) if (NumFeatures)
OS << Target << "FeatureKV, "; OS << Target << "FeatureKV, ";
@ -1482,10 +1482,11 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n"; OS << "namespace llvm {\n";
OS << "class DFAPacketizer;\n"; OS << "class DFAPacketizer;\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "(StringRef TT, StringRef CPU, " << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS);\n" << "StringRef FS);\n"
<< "public:\n" << "public:\n"
<< " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI," << " unsigned resolveSchedClass(unsigned SchedClass, "
<< " const MachineInstr *DefMI,"
<< " const TargetSchedModel *SchedModel) const override;\n" << " const TargetSchedModel *SchedModel) const override;\n"
<< " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
<< " const;\n" << " const;\n"
@ -1515,7 +1516,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
} }
OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS)\n" << "StringRef FS)\n"
<< " : TargetSubtargetInfo() {\n" << " : TargetSubtargetInfo() {\n"
<< " InitMCSubtargetInfo(TT, CPU, FS, "; << " InitMCSubtargetInfo(TT, CPU, FS, ";